Cypress CY7C63513C manual Encoding, What the SIE does to Mode bits PID Status bits Interrupt?

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CY7C63413C

CY7C63513C

CY7C63613C

Figure 7. Decode table forTable 29: “Details of Modes for Differing Traffic Conditions”

 

 

Properties of incoming packet

 

 

 

 

 

 

 

 

Encoding

 

 

 

Status bits

 

 

What the SIE does to Mode bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PID Status bits

 

 

Interrupt?

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

End Point

 

 

 

 

 

 

 

 

 

End Point

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode

 

 

 

 

 

 

 

 

 

 

Mode

 

 

 

3

1 0

Token

count buffer dval

DTOG DVAL

Set-

In

Out

ACK

3 2

Re-

In

2

COUNT up

1 0 sponse

t

Setup

In

Out

The validity of the received data

The quality status of the DMA buffer

The number of received bytes

Legend:

UC: unchanged

TX: transmit

 

x: don’t care

RX: receive

Acknowledge phase completed

TX0: transmit 0-length packet

available for Control endpoint only

The response of the SIE can be summarized as follows:

1.the SIE will only respond to valid transactions, and will ig- nore non-valid ones;

2.the SIE will generate IRQ when a valid transaction is completed or when the DMA buffer is corrupted

3.an incoming Data packet is valid if the count is <= 10 (CRC inclusive) and passes all error checking;

4.a Setup will be ignored by all non-Control endpoints (in appropriate modes);

5.an In will be ignored by an Out configured endpoint and vice versa.

The In and Out PID status is updated at the end of a trans- action.

The Setup PID status is updated at the beginning of the Data packet phase.

The entire EndPoint 0 mode and the Count register are locked to CPU writes at the end of any transaction in which an ACK is transferred. These registers are only unlocked upon a CPU read of these registers, and only if that read happens after the transaction completes. This represents about a 1-s window to which to the CPU is locked from register writes to these USB registers. Normally the firmware does a register read at the beginning of the ISR to unlock and get the mode register infor- mation. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction.

Document #: 38-08027 Rev. *B

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Contents Functional Overview FeaturesCypress Semiconductor Corporation CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Pin Definitions Programming ModelMOV A,DSPINIT Bit Data Stack Pointer DSPAddress Modes Buttons EQU 10h MOV A,buttonsInstruction Set Summary Operand Opcode CyclesReserved Memory OrganizationProgram Memory Organization Program Memory begins hereData Memory Organization Register Name Address Read/Write Function Register SummaryO Register Summary USB Address A, Endpoint 0 counter registerReset ClockingAddr Port 1 Data General Purpose I/O PortsPin Addr Port 2 DataGpio Configuration Port Port 0 Interrupt EnableGpio Interrupt Enable Ports Addr Port 0 Interrupt EnableDAC Port + defaultAddr Gpio Configuration Register Cmos OutputDAC Port Interrupts DAC Port Interrupt EnableAddr DAC Port Interrupt Enable DAC Isink RegistersUSB Serial Interface Engine SIE USB Device Data 0/1 USB Device Counter RegistersAddr 0x11, 0x13 USB Device Counter Registers Byte countAddr Timer Register LSB Bit Free-running TimerTimer LSB Timer Register Timer MSB Timer Register Addr Timer Register MSBInterrupts Global Interrupt Enable Register AddrUSB End Point Interrupt Enable Register Addr Gpio DACInterrupt Vector Number ROM Address Function Interrupt VectorsInterrupt Vector Assignments Interrupt LatencyEncoding USB Register Mode EncodingTruth Tables NAKWhat the SIE does to Mode bits PID Status bits Interrupt? EncodingControl Write Set End Point ModeSetup Packet if accepting Control ReadOut endpoint Parameter Min Max Unit Conditions General Power-On ResetAbsolute Maximum Ratings USB InterfaceSwitching Characteristics Differential Data Lines Package Package Type Operating Size Ordering InformationOrdering Code RangeDie Pad Locations DIe Pad Locations in microns Pad # Pin NameLead Shrunk Small Outline Package SP48 Package DiagramsLead 600-Mil Molded DIP P2 Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3 PIN 1 IDDSG Issue Orig. Description of Change DateDocument History TYJ

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.