Cypress CY7C027AV, CY7C037AV, CY7C037V, CY7C028V, CY7C027VN, CY7C038V manual CY7C027V/027VN/027AV/028V

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		CY7C027V/027VN/027AV/028V
			CY7C037V/037AV/038V
Switching Waveforms(continued)
	Figure 9. Semaphore Read After Write Timing, Either Side[29]
		tSAA	tOHA
A0–A 2	VALID ADRESS	VALID ADRESS
	tAW	tACE
	tHA	tACE
SEM	tHA
SEM	tSCE	tSOP
	tSCE	tSOP
	tSD
I/O 0	DATAIN VALID		DATAOUT VALID
	DATAIN VALID		DATAOUT VALID
tSA	tHD
tSA	tPWE
R/W
	tSWRD	tDOE
OE		tSOP
	WRITE CYCLE	READ CYCLE

Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]

A0L –A2L

R/WL

SEML

A0R–A2R

MATCH

tSPS

R/WR

Notes

29.CE = HIGH for the duration of the above timing (both write and read cycle).

30.I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

31.Semaphores are reset (available to both ports) at cycle start.

32.If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.

Document #: 38-06078 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Pin Tqfp Top View Pin ConfigurationsParameter Unit Maximum Access Time Typical Operating CurrentSelection Guide Functional Description Pin DefinitionsArchitecture Semaphore Operation BusyMaster/Slave Capacitance5 Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeWrite Cycle Switching Characteristics Over the Operating Range6Including scope and jig Read CycleSemaphore Timing Data Retention ModeTiming Interrupt TimingRead Cycle No Either Port Address Access15, 16 Switching WaveformsWrite Cycle No R/W Controlled Timing 20, 21, 22 CY7C027V/027VN/027AV/028V Timing Diagram of Read with Busy M/S=HIGH33 Right Address Valid First CER ValidFirstLeft Side Clears INT L Right Side Clears INT RRight Side Sets Intl Left Port Right Port Function Non-Contending Read/Write Inputs Outputs 9 -I/O 0 -I/OOperation Interrupt Operation Example assumes32K x18 3.3V Asynchronous Dual-Port Sram Ordering Information32K x16 3.3V Asynchronous Dual-Port Sram 64K x16 3.3V Asynchronous Dual-Port SramPin Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions