Cypress CY7C038V, CY7C037AV, CY7C037V, CY7C027V, CY7C028V CER ValidFirst, Right Address Valid First

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Switching Waveforms(continued)

Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34]

CELValid First:

ADDRESS L,R

CEL

CER

BUSYR

CER ValidFirst:

ADDRESSL,R

CER

CE L

BUSYL

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH
tPS
tBLC	tBHC

Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[34]

Left Address Valid First:

ADDRESSL

ADDRESSR

BUSY R

tRC or tWC

ADDRESS MATCH ADDRESS MISMATCH

tPS

tBLA tBHA

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSY L

tRC or tWC

ADDRESS MATCH ADDRESS MISMATCH

tPS

tBLA tBHA

Note

34. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.

Document #: 38-06078 Rev. *B Page 13 of 18

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