Cypress CY7C027V, CY7C037AV manual Ordering Information, 32K x16 3.3V Asynchronous Dual-Port Sram

Page 16

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Ordering Information

32K x16 3.3V Asynchronous Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

15

CY7C027V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C027V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C027VN-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

20

CY7C027V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C027V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

25

CY7C027V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C027V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C027AV-25AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

 

 

 

 

 

64K x16 3.3V Asynchronous Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

15

CY7C028V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C028V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

20

CY7C028V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C028V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C028V-20AI

A100

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C028V-20AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

 

 

 

 

 

25

CY7C028V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C028V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

32K x18 3.3V Asynchronous Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

15

CY7C037V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C037V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

20

CY7C037V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C037AV-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

25

CY7C037V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C037V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

64K x18 3.3V Asynchronous Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

 

(ns)

Name

Range

 

15

CY7C038V-15AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

 

CY7C038V-15AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

20

CY7C038V-20AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

 

CY7C038V-20AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

 

CY7C038V-20AI

A100

100-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

 

 

CY7C038V-20AXI

A100

100-Pin Pb-Free Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

 

25

CY7C038V-25AC

A100

100-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

 

CY7C038V-25AXC

A100

100-Pin Pb-Free Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

 

Document #: 38-06078 Rev. *B

 

 

Page 16 of 18

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court Pin Configurations Pin Tqfp Top ViewSelection Guide Maximum Access Time Typical Operating CurrentParameter Unit Architecture Pin DefinitionsFunctional Description Master/Slave BusySemaphore Operation Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Capacitance5Switching Characteristics Over the Operating Range6 Including scope and jigRead Cycle Write CycleData Retention Mode TimingInterrupt Timing Semaphore TimingSwitching Waveforms Read Cycle No Either Port Address Access15, 16Write Cycle No R/W Controlled Timing 20, 21, 22 CY7C027V/027VN/027AV/028V Timing Diagram of Read with Busy M/S=HIGH33 CER ValidFirst Right Address Valid FirstRight Side Sets Intl Right Side Clears INT RLeft Side Clears INT L Non-Contending Read/Write Inputs Outputs 9 -I/O 0 -I/O OperationInterrupt Operation Example assumes Left Port Right Port FunctionOrdering Information 32K x16 3.3V Asynchronous Dual-Port Sram64K x16 3.3V Asynchronous Dual-Port Sram 32K x18 3.3V Asynchronous Dual-Port SramPackage Diagram Pin Pb-Free Thin Plastic Quad Flat Pack Tqfp A100Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History