Cypress CY7C037AV, CY7C037V Right Side Clears INT R, Right Side Sets Intl, Left Side Clears INT L

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Figure 15. Interrupt Timing Diagrams

tWC

ADDRESSL

WRITE 7FFF (FFFF for CY7C028V/38V)

tHA[35]

CE L

R/WL

INTR

ADDRESSR

CE R

R/WR

INTL

tWC

WRITE 7FFE (FFFE for CY7C028V/38V)

tHA[35]

tINS[36]

Left Side Clears INT L:	tRC

Notes

35.tHA depends on which enable pin (CEL or R/WL) is deasserted first.

36.tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Document #: 38-06078 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Pin Configurations Pin Tqfp Top ViewParameter Unit Maximum Access Time Typical Operating CurrentSelection Guide Functional Description Pin DefinitionsArchitecture Semaphore Operation BusyMaster/Slave Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance5Read Cycle Switching Characteristics Over the Operating Range6Including scope and jig Write CycleInterrupt Timing Data Retention ModeTiming Semaphore TimingSwitching Waveforms Read Cycle No Either Port Address Access15, 16Write Cycle No R/W Controlled Timing 20, 21, 22 CY7C027V/027VN/027AV/028V Timing Diagram of Read with Busy M/S=HIGH33 CER ValidFirst Right Address Valid FirstLeft Side Clears INT L Right Side Clears INT RRight Side Sets Intl Interrupt Operation Example assumes Non-Contending Read/Write Inputs Outputs 9 -I/O 0 -I/OOperation Left Port Right Port Function64K x16 3.3V Asynchronous Dual-Port Sram Ordering Information32K x16 3.3V Asynchronous Dual-Port Sram 32K x18 3.3V Asynchronous Dual-Port SramPackage Diagram Pin Pb-Free Thin Plastic Quad Flat Pack Tqfp A100Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions