Cypress CY7C038V, CY7C037AV Maximum Ratings, Electrical Characteristics Over the Operating Range

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature............................................with

–55°C to +125°C

Power Applied

Supply Voltage to Ground Potential

–0.5V to +4.6V

DC Voltage Applied to

 

Outputs in High-Z State

–0.5V to VCC+0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage[2]

..................................

–0.5V to VCC+0.5V

Output Current into Outputs (LOW)

20 mA

Static Discharge Voltage

> 1100V

Latch-up Current

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

 

 

Range

 

Temperature

 

VCC

Commercial

 

0°C to +70°C

 

3.3V ± 300 mV

 

 

 

 

 

Industrial[3]

 

–40°C to +85°C

 

3.3V ± 300 mV

 

 

 

 

CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V

 

Parameter

Description

 

 

 

-15

 

-20

 

 

-25

 

Unit

 

 

 

 

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

 

VOH

Output HIGH Voltage

 

 

2.4

 

 

2.4

 

 

2.4

 

 

V

 

(VCC=Min., IOH= –4.0 mA)

 

 

 

 

 

 

 

 

 

 

 

 

VOL

Output LOW Voltage (VCC=Min., IOH= +4.0 mA)

 

 

0.4

 

 

0.4

 

 

0.4

V

VIH

Input HIGH Voltage

 

 

2.2

 

 

2.2

 

 

2.2

 

 

V

VIL

Input LOW Voltage

 

 

 

 

0.8

 

 

0.8

 

 

0.8

V

IIX

Input Leakage Current

 

 

5

 

5

5

 

5

5

 

5

μA

IOZ

Output Leakage Current

 

 

–10

 

10

–10

 

10

–10

 

10

μA

ICC

Operating Current (VCC=Max. IOUT=0

Com’l.

 

125

185

 

120

175

 

115

165

mA

 

mA) Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

Ind.[3]

 

 

 

 

140

195

 

 

 

mA

ISB1

Standby Current (Both Ports TTL

Com’l.

 

35

50

 

35

45

 

30

40

mA

 

Level) CEL & CER VIH, f=fMAX

 

 

 

 

 

 

 

 

 

 

 

 

Ind.[3]

 

 

 

 

45

55

 

 

 

mA

ISB2

Standby Current (One Port TTL Level)

Com’l.

 

80

120

 

75

110

 

65

95

mA

 

CEL CER VIH, f=fMAX

 

 

 

 

 

 

 

 

 

 

 

 

Ind.[3]

 

 

 

 

85

120

 

 

 

mA

ISB3

Standby Current (Both Ports CMOS

Com’l.

 

10

250

 

10

250

 

10

250

μA

 

Level) CEL & CER VCC0.2V, f=0

 

 

 

 

 

 

 

 

 

 

 

 

 

Ind.

[3]

 

 

 

 

10

250

 

 

 

μ

 

 

 

 

 

 

 

 

 

 

A

ISB4

Standby Current (One Port CMOS Lev-

Com’l.

 

75

105

 

70

95

 

60

80

mA

 

el) CEL CER VIH, f=fMAX[4]

 

 

 

 

 

 

 

 

 

 

 

 

Ind.[3]

 

 

 

 

80

105

 

 

 

mA

Capacitance[5]

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

10

pF

 

 

VCC = 3.3V

 

 

COUT

Output Capacitance

10

pF

Notes

2.Pulse width < 20 ns.

3.Industrial parts are available in CY7C028V and CY7C038V only.

4.fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.

5.Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-06078 Rev. *B

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court Pin Configurations Pin Tqfp Top ViewMaximum Access Time Typical Operating Current Selection GuideParameter Unit Pin Definitions ArchitectureFunctional Description Busy Master/SlaveSemaphore Operation Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance5Read Cycle Switching Characteristics Over the Operating Range6Including scope and jig Write CycleInterrupt Timing Data Retention ModeTiming Semaphore TimingSwitching Waveforms Read Cycle No Either Port Address Access15, 16Write Cycle No R/W Controlled Timing 20, 21, 22 CY7C027V/027VN/027AV/028V Timing Diagram of Read with Busy M/S=HIGH33 CER ValidFirst Right Address Valid FirstRight Side Clears INT R Right Side Sets IntlLeft Side Clears INT L Interrupt Operation Example assumes Non-Contending Read/Write Inputs Outputs 9 -I/O 0 -I/OOperation Left Port Right Port Function64K x16 3.3V Asynchronous Dual-Port Sram Ordering Information32K x16 3.3V Asynchronous Dual-Port Sram 32K x18 3.3V Asynchronous Dual-Port SramPackage Diagram Pin Pb-Free Thin Plastic Quad Flat Pack Tqfp A100Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History