Cypress CY14B104M, CY14B104K manual AutoStore/Power Up Recall

Page 20

 

 

 

 

 

 

PRELIMINARY

 

 

CY14B104K, CY14B104M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AutoStore/Power Up RECALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameters

 

 

Description

 

20 ns

 

25 ns

 

45 ns

Unit

 

 

Min

 

Max

Min

 

Max

Min

 

Max

 

 

 

 

 

 

 

 

 

 

 

t

[23]

 

Power Up RECALL Duration

 

 

20

 

 

20

 

 

20

ms

HRECALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSTORE [24]

 

STORE Cycle Duration

 

 

8

 

 

8

 

 

8

ms

tDELAY [25]

 

Time Allowed to Complete SRAM Cycle

 

 

20

 

 

25

 

 

25

ns

VSWITCH

 

 

Low Voltage Trigger Level

 

 

2.65

 

 

2.65

 

 

2.65

V

tVCCRISE

 

 

VCC Rise Time

150

 

 

150

 

 

150

 

 

μs

VHDIS[14]

 

 

HSB

Output Driver Disable Voltage

 

 

1.9

 

 

1.9

 

 

1.9

V

tLZHSB

 

 

HSB

To Output Active Time

 

 

5

 

 

5

 

 

5

μs

tHHHD

 

 

HSB

High Active Time

 

 

500

 

 

500

 

 

500

ns

Switching Waveforms

Figure 12. AutoStore or Power Up RECALL[26]

VSWITCH

 

 

 

 

VHDIS

 

 

 

 

VVCCRISE

Note24

t

Note24

t

 

 

STORE

 

STORE

 

tHHHD

 

tHHHD

Note27

 

 

 

HSB OUT

 

 

tDELAY

 

 

 

 

 

 

tLZHSB

 

t

 

Autostore

 

 

LZHSB

 

 

 

 

 

 

tDELAY

 

 

 

POWER-

 

 

 

 

UP

 

 

 

 

RECALL

tHRECALL

 

tHRECALL

 

 

 

 

 

Read & Write

Inhibited

(RWI)

POWER-UP Read & Write

BROWN

POWER-UP

Read & Write

POWER

RECALL

OUT

RECALL

 

DOWN

 

Autostore

 

 

Autostore

Notes

23.tHRECALL starts from the time VCC rises above VSWITCH.

24.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

25.On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

26.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

27.HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-07103 Rev. *K

Page 20 of 31

[+] Feedback

Image 20
Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Pinouts Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Hardware Store HSB OperationSoftware Recall Software StoreMode Selection A15 A06 Mode PowerPreventing AutoStore StoreReal Time Clock Operation Data ProtectionNoise Considerations Calibrating the Clock AlarmWatchdog Timer Power Monitor Interrupt RegisterInterrupts Flags RegisterWDF Watchdog Timer Flag PF Power Fail FlagPFE Power Fail Enable AF Alarm FlagWDF Oscf OscenWDS 0x7FFF9 0x3FFF9 Time Keeping Seconds For the register is0x7FFF5 0x3FFF5 Alarm Day Time-baseWatchdog Write only. Reading it always returns a0x7FFF2 0x3FFF2 Alarm Seconds Centuries 0x7FFF0 0x3FFF0 FlagsThis condition and write 0 to clear this flag Document # 001-07103 Rev. *KDC Electrical Characteristics Range Ambient TemperatureMaximum Ratings Operating RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsRTC Backup Current Hot Temperature 85 oCRTC Battery Pin Voltage RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleData Output High Impedance Output Data Valid Standby ActiveAddress Valid Data Input Input Data ValidData Input Data Output Input Data Valid High ImpedanceNot applicable for RTC register writes Address Address ValidAutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled Store and Recall Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Hardware Store Pulse WidthFor x8 Configuration For x16 ConfigurationInputs and Outputs Mode Power Truth Table For Sram OperationsNvsram Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TZS Tsop Ordering Information Package Diagrams Pin Tsop II51-85160 Document History TUPPCI UHAGVCH/PYRS Added 20 ns access speed in Features Footnote 1 and 8 referenced for Mode selection Table6 updated Data protection description 6 Updated Starting and stopping the oscillator descriptionUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions