PRELIMINARY | CY14B104K, CY14B104M |
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Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
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Rev. | ECN No. | Submission | Orig. of |
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| Description of Change |
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| Date | Change |
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*I | 2519319 | 06/20/08 | GVCH/PYRS | Added 20 ns access speed in “Features” |
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| Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade | |||||||||
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| Updated Thermal resistance values for | |||||||||
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| Added AC Switching Characteristics specs for 20 ns access speed | |||||||||
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| Added Software controlled STORE/RECALL cycle specs for 20 ns access speed | |||||||||
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| Updated ordering information and Part numbering nomenclature | |||||||||
*J | 2600941 | 11/04/08 | GVCH/PYRS | Removed 15 ns access speed from “Features” |
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| Changed part number from CY14B104K/CY14B104M to | |||||||||
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| CY14B104KA/CY14B104MA | |||||||||
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| Updated Logic block diagram | |||||||||
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| Updated footnote 1 | |||||||||
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| Added footnote 2 | |||||||||
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| Pin definition: Updated | WE, |
| HSB | and NC pin description | |||||
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| Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description | |||||||||
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| Page 4: Updated Hardware store operation and Hardware RECALL (Power up) | |||||||||
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| description | |||||||||
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| Footnote 1 and 8 referenced for Mode selection Table | |||||||||
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| Updated footnote 6 | |||||||||
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| Page 6: updated Data protection description | |||||||||
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| Page 6: Updated Starting and stopping the oscillator description | |||||||||
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| Page 7: Updated Calibrating the clock description | |||||||||
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| Page 7: Updated Alarm description | |||||||||
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| Page 8: Added Flags register | |||||||||
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| Added footnote 10 and 11 | |||||||||
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| Updated Figure 4: Removed RF register and Changed C2 value from 56pF to | |||||||||
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| 12pF | |||||||||
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| Updated Register Map Table 3 | |||||||||
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| Updated Register map detail Table 4 | |||||||||
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| Maximum Ratings: Added Max. Accumulated storage time | |||||||||
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| Changed Output short circuit current parameter name to DC output current | |||||||||
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| Changed ICC2 from 6mA to 10mA | |||||||||
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| Changed ICC4 from 6mA to 5mA | |||||||||
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| Changed ISB from 3mA to 5mA | |||||||||
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| Updated ICC1, ICC3, ISB and IOZ Test conditions | |||||||||
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| Changed VCAP voltage max value from 82uF to 180uF | |||||||||
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| Updated footnote 12 and 13 | |||||||||
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| Added footnote 14 | |||||||||
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| Added Data retention and Endurance Table | |||||||||
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| Updated Input Rise and Fall time in AC test Conditions | |||||||||
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| Changed tOCS value for minimum temperature from 10 to 2 sec | |||||||||
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| updated tOCS value for room temperature from 5 to 1sec | |||||||||
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| Referenced footnote 20 to tOHA parameter | |||||||||
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| Updated All switching waveforms | |||||||||
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| Updated footnote 20 |
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| Added Figure 11 (SRAM WRITE CYCLE:BHE | and BLE controlled) | ||||||||
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| Updated tDELAY value | |||||||||
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| Added VHDIS, tHHHD and tLZHSB parameters | |||||||||
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| Updated footnote 27 | |||||||||
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| Added footnote 29 | |||||||||
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| Software controlled STORE/RECALL Table: Changed tAS to tSA | |||||||||
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| Changed tGHAX to tHA | |||||||||
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| Changed tHA value from 1ns to 1ns | |||||||||
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| Added tDHSB parameter | |||||||||
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| Changed tHLHX to tPHSB | |||||||||
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| Updated tSS from 70us to 100us | |||||||||
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| Added truth table for SRAM operations | |||||||||
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| Updated ordering information and part numbering nomenclature | |||||||||
Document #: |
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| Page 30 of 31 | |||
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