Cypress CY14B104K Truth Table For Sram Operations, For x8 Configuration, For x16 Configuration

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PRELIMINARY

CY14B104K, CY14B104M

Truth Table For SRAM Operations

should remain HIGH for SRAM Operations.

HSB

For x8 Configuration

CE

WE

OE

Inputs and Outputs[2]

Mode

Power

H

X

X

High Z

Deselect/Power down

Standby

L

H

L

Data Out (DQ0–DQ7);

Read

Active

L

H

H

High Z

Output Disabled

Active

L

L

X

Data in (DQ0–DQ7);

Write

Active

For x16 Configuration

CE

WE

OE

BHE

BLE

Inputs and Outputs[2]

Mode

Power

H

X

X

X

X

High-Z

Deselect/Power down

Standby

L

X

X

H

H

High-Z

Output Disabled

Active

L

H

L

L

L

Data Out (DQ0–DQ15)

Read

Active

L

H

L

H

L

Data Out (DQ0–DQ7);

Read

Active

DQ8–DQ15in High-Z

L

H

L

L

H

Data Out (DQ8–DQ15);

Read

Active

DQ0–DQ7in High-Z

L

H

H

L

L

High-Z

Output Disabled

Active

L

H

H

H

L

High-Z

Output Disabled

Active

L

H

H

L

H

High-Z

Output Disabled

Active

L

L

X

L

L

Data In (DQ0–DQ15)

Write

Active

L

L

X

H

L

Data In (DQ0–DQ7);

Write

Active

DQ8–DQ15in High-Z

L

L

X

L

H

Data In (DQ8–DQ15);

Write

Active

DQ0–DQ7in High-Z

Document #: 001-07103 Rev. *K

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Pinouts AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpHardware Store HSB Operation Software RecallStore Mode SelectionA15 A06 Mode Power Preventing AutoStoreReal Time Clock Operation Data ProtectionNoise Considerations Calibrating the Clock AlarmWatchdog Timer Flags Register Power MonitorInterrupt Register InterruptsAF Alarm Flag WDF Watchdog Timer FlagPF Power Fail Flag PFE Power Fail EnableWDF Oscf OscenWDS For the register is 0x7FFF9 0x3FFF9 Time Keeping SecondsWrite only. Reading it always returns a 0x7FFF5 0x3FFF5 Alarm DayTime-base WatchdogDocument # 001-07103 Rev. *K 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags This condition and write 0 to clear this flagOperating Range DC Electrical CharacteristicsRange Ambient Temperature Maximum RatingsAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceRTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start RTC Backup CurrentHot Temperature 85 oC RTC Battery Pin VoltageSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleData Input Input Data Valid Data Output High Impedance Output Data ValidStandby Active Address ValidAddress Address Valid Data Input Data OutputInput Data Valid High Impedance Not applicable for RTC register writesParameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled Store and Recall Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit MinTruth Table For Sram Operations For x8 ConfigurationFor x16 Configuration Inputs and Outputs Mode PowerNvsram Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TZS Tsop Ordering Information Pin Tsop II Package Diagrams51-85160 UHA Document HistoryTUP PCIGVCH/PYRS 6 Updated Starting and stopping the oscillator description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 updated Data protection descriptionUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions