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| PRELIMINARY | CY14B104K, CY14B104M | |
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Data Protection |
| Setting the Clock |
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The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B104K/CY14B104M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Real Time Clock Operation
nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B104K in the following sections. The same description applies to CY14B104M, except for the RTC register addresses. The RTC register addresses for CY14B104K range from 0x7FFF0 to 0x7FFFF, while those for CY14B104M range from 0x3FFF0 to 0x3FFFF. Refer to Table 4 on page 10 and Table 5 on page 11 for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress.
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’ stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24 hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time. Resetting the write bit to ‘0’ transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation.
If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation.
Note The values entered in the timekeeping, alarm, calibration, and interrupt registers need a STORE operation to be saved in nonvolatile memory. Therefore, while working in AutoStore disabled mode, the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly.
Backup Power
The RTC in the CY14B104K is intended for permanently powered operation. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost.
During backup operation, the CY14B104K consumes a maximum of 300 nanoamps at room temperature. User must choose capacitor or battery values according to the application.
Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer.
Table 3. RTC Backup Time
Capacitor Value | Backup Time |
0.1F | 72 hours |
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0.47F | 14 days |
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1.0F | 30 days |
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Reading the Clock
The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. The user must stop internal updates to the CY14B104K time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit ‘R’ (in the flags register at 0x7FFF0), and does not restart until a ‘0’ is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a ‘0’ is written to the read bit (‘R’), all RTC registers are simultaneously updated within 20 ms
Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14B104K sources current only from the battery when the primary power is removed. However the battery is not recharged at any time by the CY14B104K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to 0) state. To preserve the battery life when the system is in storage, OSCEN
Document #: | Page 6 of 31 |
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