Cypress CY14B104M, CY14B104K manual Document History, Tup, Pci, Uha

Page 28

PRELIMINARY

CY14B104K, CY14B104M

 

Document History Page

Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

Document Number: 001-07103

Rev.

ECN No.

Submission

Orig. of

Description of Change

 

 

Date

Change

 

 

 

 

 

**

431039

See ECN

TUP

New Data Sheet

*A

489096

See ECN

TUP

Removed 48 SSOP Package

 

 

 

 

Added 44 TSOPII and 54 TSOPII Packages

 

 

 

 

Updated Part Numbering Nomenclature and Ordering Information

 

 

 

 

Added Soft Sequence Processing Time Waveform

 

 

 

 

Added RTC Characteristics Table

 

 

 

 

Added RTC Recommended Component Configuration

*B

499597

See ECN

PCI

Removed 35ns speed bin

 

 

 

 

Added 55ns speed bin. Updated AC table for the same

 

 

 

 

Changed “Unlimited” read/write to “infinite” read/write

 

 

 

 

Features section: Changed typical ICC at 200-ns cycle time to 8 mA

 

 

 

 

Changed STORE cycles from 500K to 200K cycles.

 

 

 

 

Shaded Commercial grade in operating range table.

 

 

 

 

Modified Icc/Isb specs.

 

 

 

 

Changed VCAP value in DC table

 

 

 

 

Added 44 TSOP II in Thermal Resistance table

 

 

 

 

Modified part nomenclature table. Changes reflected in the ordering information

 

 

 

 

table.

*C

517793

See ECN

TUP

Removed 55ns speed bin

 

 

 

 

Changed pinout for 44TSOPII and 54TSOPII packages

 

 

 

 

Changed ISB to 1mA

 

 

 

 

Changed ICC4 to 3mA

 

 

 

 

Changed VCAP min to 35μF

 

 

 

 

Changed VIH max to Vcc + 0.5V

 

 

 

 

Changed tSTORE to 15ns

 

 

 

 

Changed tPWE to 10ns

 

 

 

 

Changed tSCE to 15ns

 

 

 

 

Changed tSD to 5ns

 

 

 

 

Changed tAW to 10ns

 

 

 

 

Removed tHLBL

 

 

 

 

 

 

 

 

Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW

 

 

 

 

Removed min. specification for Vswitch

 

 

 

 

Changed tGLAX to 1ns

 

 

 

 

Added tDELAY max. of 70us

 

 

 

 

Changed tSS specification from 70us min. to 70us max.

*D

825240

See ECN

UHA

Changed the data sheet from Advance information to Preliminary

 

 

 

 

Changed tDBE to 10ns in 15ns part

 

 

 

 

Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns

 

 

 

 

Changed tBW in 15ns part to 15ns and in 25ns part to 20ns

 

 

 

 

Changed tGLAX to tGHAX

 

 

 

 

Changed the value of ICC3 to 25mA

 

 

 

 

Changed the value of tAW in 15ns part to 15ns

*E

914280

See ECN

UHA

Changed the figure-14 title from 54-Pb to 54 Pin

 

 

 

 

Included all the information for 45ns part in this data sheet

Document #: 001-07103 Rev. *K

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Pinouts Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Hardware Store HSB OperationSoftware Recall Software StoreMode Selection A15 A06 Mode PowerPreventing AutoStore StoreNoise Considerations Data ProtectionReal Time Clock Operation Watchdog Timer AlarmCalibrating the Clock Power Monitor Interrupt RegisterInterrupts Flags RegisterWDF Watchdog Timer Flag PF Power Fail FlagPFE Power Fail Enable AF Alarm FlagWDS OscenWDF Oscf 0x7FFF9 0x3FFF9 Time Keeping Seconds For the register is0x7FFF5 0x3FFF5 Alarm Day Time-baseWatchdog Write only. Reading it always returns a0x7FFF2 0x3FFF2 Alarm Seconds Centuries 0x7FFF0 0x3FFF0 FlagsThis condition and write 0 to clear this flag Document # 001-07103 Rev. *KDC Electrical Characteristics Range Ambient TemperatureMaximum Ratings Operating RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsRTC Backup Current Hot Temperature 85 oCRTC Battery Pin Voltage RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleData Output High Impedance Output Data Valid Standby ActiveAddress Valid Data Input Input Data ValidData Input Data Output Input Data Valid High ImpedanceNot applicable for RTC register writes Address Address ValidAutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled Store and Recall Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Hardware Store Pulse WidthFor x8 Configuration For x16 ConfigurationInputs and Outputs Mode Power Truth Table For Sram OperationsZS Tsop Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TNvsram Ordering Information Package Diagrams Pin Tsop II51-85160 Document History TUPPCI UHAGVCH/PYRS Added 20 ns access speed in Features Footnote 1 and 8 referenced for Mode selection Table6 updated Data protection description 6 Updated Starting and stopping the oscillator descriptionWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB