Cypress CY14B104M, CY14B104K manual Package Diagrams, Pin Tsop II

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PRELIMINARY	CY14B104K, CY14B104M

Package Diagrams

	Figure 17.		44-Pin TSOP II (51-85087)
22	1	PIN 1 I.D.
22	1
	11.938 (0.470)	11.735 (0.462)	10.262 (0.404)	10.058 (0.396)
23	44

DIMENSION IN MM (INCH)

MAX

MIN.

O R E

K X A

S G

EJECTOR PIN

TOP VIEW

BOTTOM VIEW

0.800 BSC	0.400(0.016)
	0.300 (0.012)	BASE PLANE
(0.0315)

0° -5°

0.10 (.004)

18.517 (0.729)

18.313 (0.721)

(0.047)1.194	(0.039)0.991	(0.0059)0.150	(0.0020)0.050	SEATING

				PLANE

10.262 (0.404)

10.058 (0.396)

0.597 (0.0235)

0.406 (0.0160)

0.210 (0.0083)

0.120 (0.0047)

51-85087 *A

Document #: 001-07103 Rev. *K

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Pinouts Sram Write Device OperationSram Read AutoStore OperationSoftware Recall Hardware Recall Power UpHardware Store HSB Operation Software StorePreventing AutoStore Mode SelectionA15 A06 Mode Power StoreReal Time Clock Operation Data ProtectionNoise Considerations Calibrating the Clock AlarmWatchdog Timer Interrupts Power MonitorInterrupt Register Flags RegisterPFE Power Fail Enable WDF Watchdog Timer FlagPF Power Fail Flag AF Alarm FlagWDF Oscf OscenWDS 0x7FFF9 0x3FFF9 Time Keeping Seconds For the register isWatchdog 0x7FFF5 0x3FFF5 Alarm DayTime-base Write only. Reading it always returns aThis condition and write 0 to clear this flag 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags Document # 001-07103 Rev. *KMaximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsRTC Battery Pin Voltage RTC Backup CurrentHot Temperature 85 oC RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleAddress Valid Data Output High Impedance Output Data ValidStandby Active Data Input Input Data ValidNot applicable for RTC register writes Data Input Data OutputInput Data Valid High Impedance Address Address ValidAutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled Store and Recall Cycle Description 20 ns 25 ns 45 ns Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthInputs and Outputs Mode Power For x8 ConfigurationFor x16 Configuration Truth Table For Sram OperationsNvsram Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TZS Tsop Ordering Information Package Diagrams Pin Tsop II51-85160 PCI Document HistoryTUP UHAGVCH/PYRS 6 updated Data protection description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 Updated Starting and stopping the oscillator descriptionUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

Package Diagrams

44-Pin TSOP II (51-85087)

TOP VIEW

BOTTOM VIEW