Cypress CY14B104K, CY14B104M manual Data Retention and Endurance, Capacitance, Thermal Resistance

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PRELIMINARY

CY14B104K, CY14B104M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Retention and Endurance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

Description

 

 

 

Min

 

 

 

 

 

Unit

DATAR

 

 

Data Retention

 

 

 

20

 

 

 

 

 

Years

NVC

 

 

Nonvolatile STORE Operations

 

200

 

 

 

 

 

 

K

Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In the following table, the capacitance parameters are listed. [14]

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

Description

 

 

Test Conditions

 

Max

 

Unit

CIN

 

Input Capacitance

 

TA = 25°C, f = 1 MHz,

 

 

 

 

7

 

 

pF

 

 

 

 

VCC = 0 to 3.0V

 

 

 

 

 

 

 

 

 

 

COUT

 

Output Capacitance

 

 

 

 

 

7

 

 

pF

Thermal Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In the following table, the thermal resistance parameters are listed.[14]

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

Description

 

Test Conditions

 

 

44 TSOP II

 

54 TSOP II

Unit

 

 

ΘJA

Thermal Resistance

Test conditions follow standard

 

31.11

 

30.73

°C/W

 

 

 

(Junction to Ambient)

test methods and procedures

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for measuring thermal

 

 

 

 

 

 

 

 

 

 

 

ΘJC

Thermal Resistance

 

 

5.56

 

6.08

°C/W

 

 

impedance, in accordance

 

 

 

 

 

(Junction to Case)

with EIA/JESD51.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6. AC Test Loads

 

 

 

 

 

 

 

 

 

 

 

3.0V

577Ω

3.0V

R1

 

OUTPUT

OUTPUT

 

30 pF

R2

5 pF

 

789Ω

 

577Ω

R1

R2 789Ω

AC Test Conditions

Input Pulse Levels

0V to 3V

Input Rise and Fall Times (10% - 90%)

<3 ns

Input and Output Timing Reference Levels

1.5V

Note

14. These parameters are only guaranteed by design and are not tested.

Document #: 001-07103 Rev. *K

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Pinouts AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpHardware Store HSB Operation Software RecallStore Mode SelectionA15 A06 Mode Power Preventing AutoStoreData Protection Noise ConsiderationsReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Flags Register Power MonitorInterrupt Register InterruptsAF Alarm Flag WDF Watchdog Timer FlagPF Power Fail Flag PFE Power Fail EnableOscen WDSWDF Oscf For the register is 0x7FFF9 0x3FFF9 Time Keeping SecondsWrite only. Reading it always returns a 0x7FFF5 0x3FFF5 Alarm DayTime-base WatchdogDocument # 001-07103 Rev. *K 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags This condition and write 0 to clear this flagOperating Range DC Electrical CharacteristicsRange Ambient Temperature Maximum RatingsAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceRTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start RTC Backup CurrentHot Temperature 85 oC RTC Battery Pin VoltageSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleData Input Input Data Valid Data Output High Impedance Output Data ValidStandby Active Address ValidAddress Address Valid Data Input Data OutputInput Data Valid High Impedance Not applicable for RTC register writesParameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled Store and Recall Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit MinTruth Table For Sram Operations For x8 ConfigurationFor x16 Configuration Inputs and Outputs Mode PowerPart Numbering Nomenclature CY14 B 104 K ZS P 20 X C T ZS TsopNvsram Ordering Information Pin Tsop II Package Diagrams51-85160 UHA Document HistoryTUP PCIGVCH/PYRS 6 Updated Starting and stopping the oscillator description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 updated Data protection descriptionSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB