Cypress CY14B104K AC Switching Characteristics, Switching Waveforms, Parameters Sram Read Cycle

		PRELIMINARY		CY14B104K, CY14B104M
AC Switching Characteristics
Parameters		Description	20 ns		25 ns		45 ns		Unit
Cypress	Alt		Min	Max	Min	Max	Min	Max
Parameters	Parameters
SRAM Read Cycle
tACE	tACS	Chip Enable Access Time		20		25		45	ns
tRC [16]	tRC	Read Cycle Time	20		25		45		ns
tAA [17]	tAA	Address Access Time		20		25		45	ns
tDOE	tOE	Output Enable to Data Valid		10		12		20	ns
tOHA[17]	tOH	Output Hold After Address Change	3		3		3		ns
tLZCE [14, 18]	tLZ	Chip Enable to Output Active	3		3		3		ns
tHZCE [14, 18]	tHZ	Chip Disable to Output Inactive		8		10		15	ns
tLZOE [14, 18]	tOLZ	Output Enable to Output Active	0		0		0		ns
tHZOE [14, 18]	tOHZ	Output Disable to Output Inactive		8		10		15	ns
tPU [14]	tPA	Chip Enable to Power Active	0		0		0		ns
tPD [14]	tPS	Chip Disable to Power Standby		20		25		45	ns
tDBE	-	Byte Enable to Data Valid		10		12		20	ns
tLZBE[14]	-	Byte Enable to Output Active	0		0		0		ns
tHZBE[14]	-	Byte Disable to Output Inactive		8		10		15	ns
SRAM Write Cycle
tWC	tWC	Write Cycle Time	20		25		45		ns
tPWE	tWP	Write Pulse Width	15		20		30		ns
tSCE	tCW	Chip Enable To End of Write	15		20		30		ns
tSD	tDW	Data Setup to End of Write	8		10		15		ns
tHD	tDH	Data Hold After End of Write	0		0		0		ns
tAW	tAW	Address Setup to End of Write	15		20		30		ns
tSA	tAS	Address Setup to Start of Write	0		0		0		ns
tHA	tWR	Address Hold After End of Write	0		0		0		ns
tHZWE [14, 18,19]	tWZ	Write Enable to Output Disable		8		10		15	ns
tLZWE [14, 18]	tOW	Output Active after End of Write	3		3		3		ns
tBW	-	Byte Enable to End of Write	15		20		30		ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled[16, 17, 20]

	tRC
Address	Address Valid
	tAA
Data Output	Previous Data Valid
	tOHA

Notes

16.WE must be HIGH during SRAM read cycles.

17.Device is continuously selected with CE, OE and BHE / BLE LOW.

18.Measured ±200 mV from steady state output voltage.

19.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

20.HSB must remain HIGH during READ and WRITE cycles.

Output Data Valid

Document #: 001-07103 Rev. *K Page 17 of 31

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