American Telecom AM64/128A manual Mrac Connector Pin allocation

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Appendix A - Interface Connections

AM64/128A User Manual

 

 

V.35 (MRAC) Connector Pin allocation

Note: Circuit 108/1 is not available on the connector as an interface line but is software clamped in the ON state.

 

Pin

 

 

 

TYPE

Unbal

A wire

B wire

Circuit

Description

SITS 89/43

 

 

 

 

 

 

B

 

 

102

Common Return

Common

 

P

S

103

Transmitted Data

Load

 

R

T

104

Received Data

Generator

C

 

 

105

Request to Send

Load

D

 

 

106

Ready for Sending

Generator

E

 

 

107

Data Set Ready

Generator

F

 

 

109

Data Channel Received

Generator

 

U

W

113

External Transmitter Signal Element Timing

Load

 

Y

AA*

114

Transmitter Signal Element Timing

Generator

 

V

X

115

Receiver Signal Element Timing

Generator

N

 

 

140

Remote Loopback

Load

L

 

 

141

Local Loopback

Load

NN*

 

 

142

Test Indicator

Generator

 

 

 

 

 

 

Note that on some MRAC connectors pin ‘AA’ is marked as ‘a’ and pin ‘NN’ is marked ‘m’.

37 Way D-type V.36 Connector pin allocation

 

Pin

 

 

 

TYPE

Unbal

A wire

B wire

Circuit

Description

SITS 89/43

 

 

 

 

 

 

19, 20, 27, 29, 31

102

Common Return

Common

 

 

 

103

 

 

 

4

22

Transmitted Data

Load

 

6

24

104

Received Data

Generator

 

7

25

105*

Request to Send

Load

9

(9)

(27)

106*

Ready for Sending

Generator

11

(11)

(29)

107*

Data Set Ready

Generator

13

(13)

(31)

109*

Data Channel Received

Generator

 

17

35

113

External Transmitter Signal Element Timing

Load

 

5

23

114

Transmitter Signal Element Timing

Generator

 

8

26

115

Receiver Signal Element Timing

Generator

14

 

 

140

Remote Loopback

Load

10

 

 

141

Local Loopback

Load

18

 

 

142

Test Indicator

Generator

 

 

 

 

 

 

*Standards indicate that the control circuits 105,106,107,109 may be implemented as balanced circuits (using both A and B wires) or unbalanced single ended circuits. In the case of the control circuits the A wire is to be used and the B wire is to be joined to GND (circuit 102) at the receiver end of the circuit. In the AM64/128A circuit 105 is implemented as a balanced circuit and 106,107,109 are unbalanced.

A-2

Image 41
Contents Base Band Modem ATL Part No /203/002/610 Issue 4 SeptemberInformation Contained This Document is Confidential to Contents Appendix B International Models IntroductionInterface Modules Constructional DetailsBaseband Modems System Overview System Overview Testing InstallationBBM to BBM Link Self Test PassLink Mode LTU Ready No Alarm LTU Not ReadyBBM to Line Card Link Network ModeMenu Operation Front Panel FeaturesLoop back On Loop back OffLoop Active Status MenuOver all Status No Alarm No Signal Receiving AIS No Alignment Alarm StatusLOS/CD Fail CD FailInterface Status User RateLine Rate Link Mode Network Mode Operating ModeLocal loop Test MenuLocal loop from menu Top level display shows Loc Loop Off Loc Loop OnLocal loop from DTE LoopbackLoopback is applied by selecting the display Loopback Off Loopback OnRemote Loop from menu Remote LoopRem Loop Off Rem Loop OnBin Keys Off Sending Bin Binary PatternsRemote loop from DTE Data Test Error Count Bit Error Rate BER = User Data Rate x TimeOverview OperationErrors s000001 Errors nnnnnnErrors Data TestTransparent Mode Injection ModeInjecting 0s Injecting 1sSvc Test Service TestComms Evp Rx Evp Tx Time If the count is stopped the display is StopSelf Test Lamp TestComm Loop Off Communication Channel LoopbackRate 4.8K Rate MenuMaster 64K BT Slave 4.8K 2 X.21bis Option Menu3 G.703 Asynchronous ModeSignalling Rate Char Len Character LengthLine Rate Configuration MenuMaster Slave Synchronisation Type for software versions below 3 X.21 Loop ControlModem Ext Byte Clk Synchronisation Type for software version V1.3 and aboveExt Bit Clk Internal ClkMenu Lock 5 64k ModePower Level Glossary of Terms Band circuits General Specifications Appendix a Interface Pin Connections Way D type X.21 bis V.24 / V.28* Connector pin allocationWay D-type X.21 V.11 Connector pin allocation Way D-type V.36 Connector pin allocation Mrac Connector Pin allocationLine Connector Way D-type RS-530 Connector pin allocationAppendix B Internal Link Settings Page Interface Module Interface Modules21bis Interface Module RS530 Interface ModuleFrame Structure Service Test FacilitiesAppendix C In Service Test TTE Network and Safety statements LVD Safety Statements21 bit timing cable 15 way to 15 way D type plugs Appendix E35 bit timing cable 34 way to 34 way Mrac plugs 21 byte timing cable 15 way to 15 way D type plugs24 / V.28 bit timing cable 25 way to 25 way D type plugs RS530 bit timing cable 25 way to 25 way D type plugs 21 bis V.36 bit timing cable 37 way to 37 way D type plugsAppendix F Troubleshooting Power 10dBm Slave Mode 64K RateMaster Mode C 64K Rate Rate 64K