(3) PC/104 ISA Bus Signal Description
| Name | Description |
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| BUSCLK [Output] | The BUSCLK signal of the I/O channel is asynchronous |
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| to the CPU clock. |
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| RSTDRV [Output] | This signal goes high during |
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| hardware reset |
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| SA0 - SA19 | The System Address lines run from bit 0 to 19. They are |
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| [Input / Output] | latched onto the falling edge of "BALE" |
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| LA17 - LA23 | The Unlatched Address line run from bit 17 to 23 |
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| [Input/Output] |
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| SD0 - SD15 | System Data bit 0 to 15 |
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| [Input/Output] |
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| BALE [Output] | The Buffered Address Latch Enable is used to latch SA0 |
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| – SA19 onto the falling edge. This signal is forced high |
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| during DMA cycles |
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| The I/O Channel Check is an active low signal which |
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| indicates that a parity error exist on the I/O board |
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| IOCHRDY | This signal lengthens the I/O, or memory read/write cycle, |
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| [Input, Open collector] | and should be held low with a valid address |
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| IRQ | The Interrupt Request signal indicates I/O service request |
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| [Input] | attention. They are prioritized in the following sequence : |
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| (Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest) |
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| The I/O Read signal is an active low signal which |
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| [Input/Output] | instructs the I/O device to drive its data onto the data bus |
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| The I/O write signal is an active low signal which instructs |
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| the I/O device to read data from the data bus |
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| The System Memory Read is low while any of the low |
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| 1mega bytes of memory are being used |
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| The Memory Read signal is low while any memory |
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| [Input/Output] | location is being read |
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| The System Memory Write is low while any of the low |
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| 1mega bytes of memory is being written |
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| The Memory Write signal is low while any memory |
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| [Input/Output] | location is being written |
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| DRQ | DMA Request channels 0 to 3 are for |
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| DMA Request channels 5 to 7 are for |
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| transfers. DMA request should be held high until the |
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| corresponding DMA has been completed. DMA request |
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| priority is in the following sequence:(Highest) DRQ 0, 1, |
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| 2, 3, 5, 6, 7 (Lowest) |
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| The DMA Acknowledges 0 to 3, 5 to 7 are the |
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| [Output] | corresponding acknowledge signals for DRQ 0 to 3 and 5 |
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| to 7 |
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| AEN [output] | The DMA Address Enable is high when the DMA |
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| controller is driving the address bus. It is low when the |
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| CPU is driving the address bus |
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| This signal is used to indicate a memory refresh cycle |
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| [Input/Output] | and can be driven by the microprocessor on the I/O |
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| channel |
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| TC [Output] | Terminal Count provides a pulse when the terminal count |
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| for any DMA channel is reached |
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| SBHE [Input/Output] | The System Bus High Enable indicates the high byte SD8 |
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| - SD15 on the data bus |
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