Maxtor 92305H3, 93073H4, 96147H8 Ultra DMA Timing, Timing Parameters all times in nanoseconds

AT INTERFACE DESCRIPTION

Ultra DMA Timing

TIMING PARAMETERS (all times in nanoseconds)		MODE 0		MODE 1		MODE 2		MODE 3		MODE 4
		MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
tCYC	Cycle Time (from STROBE edge to STROBE edge)	112		73		54		39		25
t2CYC	Two cycle time (from rising edge to next rising edge or	230		154		115		86		57
	from falling edge to next falling edge of STROBE)
tD S	Data setup time (at recipient)	15		10		7		7		5
tDH	Data hold time (at recipient)	5		5		5		5		5
tDVS	Data valid setup time at sender (time from data bus being	70		48		30		20		6
	valid until STROBE edge)
tDVH	Data valid hold time at sender (time from STROBE edge	6		6		6		6		6
	until data may go invalid)
tF S	First STROBE (time for device to send first STROBE)	0	230	0	200	0	170	0	130	0	120
tL I	Limited interlock time (time allowed between an action by	0	150	0	150	0	150	0	100	0	100
	one agent, either host or device, and the following action
	by the other agent)
tMLI	Interlock time with minimum	20		20		20		20		20
tU I	Unlimited interlock time	0		0		0		0		0
tA Z	Maximum time allowed for outputs to release		10		10		10		10		10
tZAH	Minimum delay time required for output drivers turning on	20		20		20		20		20
tZAD	(from released state)	0		0		0		0		0
tENV	Envelope time (all control signal transitions are within the	20	70	20	70	20	70	20	55	20	55
	DMACK envelope by this much time)
tS R	STROBE to DMARDY (response time to ensure the		50		30		20		NA		NA
	synchronous pause case when the recipient is pausing)
tRFS	Ready-to-final-STROBE time (no more STROBE edges		75		70		60		60		60
	may be sent this long after receiving DMARDY- negation)
tR P	Ready-to-pause time (time until a recipient may assume	160		125		100		100		100
	that the sender has paused after negation of DMARDY-)
tIORDYZ	Pull-up time before allowing IORDY to be released		20		20		20		20		20
tZ I O R D Y	Minimum time device shall wait before driving IORDY	0		0		0		0		0
tACK	Setup and hold times before assertion and negation of	20		20		20		20		20
	DMACK-
tS S	Time from STROBE edge to STOP assertion when the	50		50		50		50		50
	sender is stopping

DMARQ
(device)
tUI
DMACK-
(host)
tA C K	tFS
	tE N V
STOP	tZAD
(host)
tA C K	tFS
	tE N V
HDMARDY-
(host)	tZAD
tZIORDY
DSTROBE
(device)
tAZ	tV D S	tDVH
DD(15:0)
tA C K
DA0, DA1, DA2,
CS0-, CS1-
	Figure 5 - 4

Initiating an Ultra DMA Data In Burst

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