Abit KV8 PRO user manual Dram Timing Selectable

3-16 Chapter 3

DRAM Timing Selectable:

Two options are available: Manual ￿ By SPD. The default setting is By SPD. When set to “By SPD”, the BIOS will read the DRAM module SPD data and automatically set to the values stored in it.

DRAM Clock:

This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up if your DRAM module does not support the clock you set.

When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM clock by the value stored in it.

CAS Latency Time:

Three options are available: 2 ￿ 2.5 ￿ 3. The default setting is 2.5. You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification.

RAS# to CAS# Delay:

This item specifies the RAS# active to CAS# read write delay time to the same bank.

Min. RAS# Active Time:

This item specifies the minimum RAS# active time.

RAS# Precharge Time:

This item specifies the RAS# precharge time.

Row Cycle Time:

This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank.

Row Refresh Cycle Time:

This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time.

RAS# to RAS# Delay:

This item specifies the RAS# active to RAS# active delay time of different bank.

Write Recovery Time:

This item specifies the time measured from the last write datum is safely registered by the DRAM.

Write to Read Delay:

This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command.

Read to Write Delay:

This item specifies the read to write delay.

KV8 Pro