Diamond Systems LX800 PC/104 Award Bios Post Codes, QNRXWVFUHHQ &OH U&026HUURUÀ J

BIOS

3.15 Award BIOS POST Codes

CFh	Test CMOS read/write functionality
C0h	Early chipset initialization: Disable shadow RAM, L2 cache (socket 7
	and below), program basic chipset registers
C1h	Detect memory: Auto detection of DRAM size, type and ECC, auto
	detection of L2 cache (socket 7 and below)
C3h	Expand compressed BIOS code to DRAM
C5h	Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01h	Expand the Xgroup codes located in physical memory address 1000:0
02h	Reserved
03h	Initial Superio_Early_Init switch
04h	Reserved
05h	%O QNRXWVFUHHQ&OH U&026HUURUÀ J
06h	Reserved
07h	Clear 8042 interface; Initialize 8042 self test
08h	Test special keyboard controller for Winbond 977 series Super I/O
	chips; Enable keyboard interface
09h	Reserved
	Disable PS/2 mouse interface (optional); Auto detect ports for
0Ah	keyboard & mouse followed by a port & interface swap (optional);
	Reset keyboard for Winbond 977 series Super I/O chips
0Bh	Reserved
0Ch	Reserved
0Dh	Reserved
0Eh	Test F000h segment shadow to see whether it is read/write capable or
	not. If test fails, keep beeping the speaker
0Fh	Reserved
10h	$XWRGHWHFWÀ VKW\SHWROR G SSURSUL WHÀ VKUH GZULWHFRGHVLQWR
	the run time area in F000 for ESCD & DMI support
11h	Reserved
12h	Use walking 1’s algorithm to check out interface in CMOS circuitry.
	Also set real time clock power status and then check for override
13h	Reserved
14h	Program chipset default values into chipset. Chipset default values
	are MODBINable by OEM customers
15h	Reserved
16h	Initial Early_Init_Onboard_Generator switch
17h	Reserved
18h	Detect CPU information including brand, SMI type (Cyrix or Intel) and
	CPU level (586 or 686)
19h	Reserved
1Ah	Reserved
	Initial interrupts vector table. ,IQRVSHFL OVSHFL¿HG OO+:
1Bh	interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to
	SPURIOUS_soft_HDLR
1Ch	Reserved
1Dh	Initial EARLY_PM_INIT switch
1Eh	Reserved
1Fh	Load keyboard matrix (notebook platform)

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