7.3.IC3 ( GDI ASIC )
IC3 (GDI ASIC)
Pin | Symbol | In/Out | Function | |
No. | ||||
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1 | PEND | Out | Paper End signal | |
2 | BUSY | Out | Busy signal | |
3 | nACK | Out | Acknowledge signal | |
4 | nSTROB | In | Data strobe signal | |
5 | VSS | - | GND | |
6 | PIOD7 | In/Out | ||
7 | VDD | - | +5V | |
8 | PIOD6 | In/Out | ||
9 | PIOD5 | In/Out | ||
10 | PIOD4 | In/Out | ||
11 | PIOD3 | In/Out | ||
12 | PIOD2 | In/Out | ||
13 | PIOD1 | In/Out | ||
14 | PIOD0 | In/Out | ||
15 | PCLK | - | N.C. | |
16 | VDD | - | +5V | |
17 | SIOAO | In/Out | GND (via 10k ohm) | |
18 | nSIOCS | - | N.C. | |
19 | SIOWR | - | N.C. | |
20 | SIORD | - | N.C. | |
21 | VDO1 | - | N.C. | |
22 | VDO0 | Out | Video data | |
23 | DOTCLK | - | N.C. | |
24 | VCLK | In | Video clock | |
25 | VSS | - | GND | |
26 | nHSYNC | In | HSYNC signal | |
27 | VDD | - | +5V | |
28 | nVSROZ | In | Engine Vsync request | |
29 | nCBSY | Out | Command busy signal | |
30 | nCCLK | Out | Communication clock | |
31 | nCMD | Out | Command data | |
32 | GIO3 | Out | Print signal | |
33 | GIO4 | In | Printer power ready signal | |
34 | GIO5 | In | Printer ready signal | |
35 | nSBSY | In | Status busy signal | |
36 | nSTS | In | Status data | |
37 | MA0 | Out | Memory address signal0 | |
38 | MA1 | Out | Memory address signal1 | |
39 | MA2 | Out | Memory address signal2 | |
40 | VSS | - | - | |
41 | MA3 | Out | Memory address signal3 | |
42 | MA4 | Out | Memory address signal4 | |
43 | VSS | - | - | |
44 | MA5 | Out | Memory address signal5 | |
45 | MA6 | Out | Memory address signal6 | |
46 | MA7 | Out | Memory address signal7 | |
47 | VDD | - | - | |
48 | MA8 | Out | Memory address signal8 | |
49 | MA9 | Out | Memory address signal9 | |
50 | nINIT | In | Initial signal | |
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KX-P7100
Pin | Symbol | In/Out | Function | |
No. | ||||
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| ||
51 | nRAS1 | Out | Memory row address strobe | |
52 | nRAS0A | Out | Bank 0 chip select signal | |
53 | nRAS0B | - | N.C. | |
54 | nCAS | Out | Memory column | |
|
|
| address strobe | |
55 | nMOE | Out | Memory output | |
|
|
| enable signal | |
56 | nMWE | Out | Memory write signal | |
57 | VSS | - | GND | |
58 | MA10 | - | N.C. | |
59 | MA11 | - | N.C. | |
60 | MA12 | - | N.C. | |
61 | MA13 | - | N.C. | |
62 | MA14 | - | N.C. | |
63 | MD7 | In/Out | Memory data7 | |
64 | VDD | - | +5V | |
65 | MD6 | In/Out | Memory data6 | |
66 | VDD | - | +5V | |
67 | MD5 | In/Out | Memory data5 | |
68 | MD4 | In/Out | Memory data4 | |
69 | MD3 | In/Out | Memory data3 | |
70 | MD2 | In/Out | Memory data2 | |
71 | MD1 | In/Out | Memory data1 | |
72 | VSS | - | GND | |
73 | MD0 | In/Out | Memory data0 | |
74 | nRD | In | CPU read signal | |
75 | nWR | In | CPU write signal | |
76 | ASTB | In | CPU latch signal | |
77 | AD0 | In/Out | CPU address/data0 | |
78 | AD1 | In/Out | CPU address/data1 | |
79 | AD2 | In/Out | CPU address/data2 | |
80 | AD3 | In/Out | CPU address/data3 | |
81 | AD4 | In/Out | CPU address/data4 | |
82 | AD5 | In/Out | CPU address/data5 | |
83 | AD6 | In/Out | CPU address/data6 | |
84 | VDD | - | +5V | |
85 | AD7 | In/Out | CPU address/data7 | |
86 | nWAIT | In/Out | +5V (via 10k ohm) | |
87 | nINTR | Out | CPU interrupt signal | |
88 | nIOCS1 | - | N.C. | |
89 | VSS | - | GND | |
90 | CLKO | - | N.C. | |
91 | CLKI | In | System clock | |
92 | VSS | - | GND | |
93 | nRESET | In | System reset signal | |
94 | CA8 | In | CPU address8 | |
95 | CA9 | In | CPU address9 | |
96 | CA10 | In | CPU address10 | |
97 | SLCTIN | In | Select In signal | |
98 | nAUTOFD | In | Auto Feed signal | |
99 | nFAULT | Out | Fault signal | |
100 | SLCT | Out | Select signal |
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