Transcend Information TS4GCF133, TS8GCF133, TS1GCF133, TS16GCF133, CF 133X, TS32GCF133 TS1G~32GCF133

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TS1G~32GCF133

133X CompactFlash Card

 

 

 

Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode.

Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode.

Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.

Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.

Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh) These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows:

Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers.

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Contents Dimensions Placement Features133X CompactFlash Card DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal DescriptionGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Resistor is optional Additional Requirements for CF Advanced Timing ModesUltra DMA Electrical Requirements 133X CompactFlash CardSeries termination required for Ultra DMA operation Table Typical Series Termination for Ultra DMAUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing Specification133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Multiple Function CompactFlash Storage Cards Card ConfigurationAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh LBA CF-ATA Command SetDefinitions Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hData Field Type Information Identify Device EchTS1G~32GCF133 0X00h Word 1 Default Number of Cylinders Word 0 General ConfigurationWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackWords 7-8 Number of Sectors per Card PIO Data Transfer Cycle Timing ModeWords 10-19 Serial Number Word 22 ECC CountTotal Sectors Addressable in LBA Mode Multiple Sector SettingMultiword DMA transfer Word 64 Advanced PIO transfer modes supportedWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 160 Power Requirement Description Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Word 128 Security StatusValue Maximum Multiword DMA timing mode supported Value Maximum PIO mode timing selectedValue Current PIO timing mode selected Word 162 Key Management Schemes SupportedValue Maximum Pcmcia IO timing mode Supported Value Current Multiword DMA timing mode selectedValue Maximum Memory timing mode Supported Idle 97h or E3hInitialize Drive Parameters 91h Idle Immediate 95h or E1hNOP 00h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS1G~32GCF133 Seek 7Xh Feature Supported Set Features EFh133X CompactFlash Card TS1G~32GCF133 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetDecription Smart Data Structure
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