Transcend Information TS8GCF133, TS4GCF133 Device Control Register Address 3F6h376h Offset Eh

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TS1G~32GCF133

133X CompactFlash Card

Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0: this bit is ignored by the CompactFlash Storage Card.

Transcend Information Inc.

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Contents 133X CompactFlash Card Placement FeaturesDimensions DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Signal Description DirGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Additional Requirements for CF Advanced Timing Modes Resistor is optionalSeries termination required for Ultra DMA operation 133X CompactFlash CardUltra DMA Electrical Requirements Table Typical Series Termination for Ultra DMAUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage CardsAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBADefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech Data Field Type InformationTS1G~32GCF133 0X00h Word 3 Default Number of Heads Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 6 Default Number of Sectors per TrackWords 10-19 Serial Number PIO Data Transfer Cycle Timing ModeWords 7-8 Number of Sectors per Card Word 22 ECC CountMultiword DMA transfer Multiple Sector SettingTotal Sectors Addressable in LBA Mode Word 64 Advanced PIO transfer modes supportedWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security StatusValue Current PIO timing mode selected Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Word 162 Key Management Schemes SupportedValue Maximum Memory timing mode Supported Value Current Multiword DMA timing mode selectedValue Maximum Pcmcia IO timing mode Supported Idle 97h or E3hNOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported133X CompactFlash Card TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register ValuesSmart Data Structure Decription