Transcend Information TS8GCF133, TS4GCF133, TS1GCF133, TS16GCF133, CF 133X, TS32GCF133 Inpack

Page 8

TS1G~32GCF133

 

133X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

Dir.

Pin

Description

-INPACK

O

43

This signal is not used in this mode.

(PC Card Memory Mode)

 

 

 

 

-INPACK

 

 

The Input Acknowledge signal is asserted by the CompactFlash Storage Card

(PC Card I/O Mode)

 

 

when the card is selected and responding to an I/O read cycle at the address that

Input Acknowledge

 

 

is on the address bus. This signal is used by the host to control the enable of any

 

 

 

 

input data buffers between the CompactFlash Storage Card and the CPU.

DMARQ

 

 

This signal is a DMA Request that is used for DMA data transfers between host

 

 

and device. It shall be asserted by the device when it is ready to transfer data to

(True IDE Mode)

 

 

 

 

or from the host. For Multiword DMA transfers, the direction of data transfer is

 

 

 

 

 

 

 

 

controlled by -IORD and -IOWR. This signal is used in a handshake manner with

 

 

 

 

-DMACK, i.e., the device shall wait until the host asserts -DMACK before

 

 

 

 

negating DMARQ, and reasserting DMARQ if there is more data to transfer.

 

 

 

 

DMARQ shall not be driven when the device is not selected.

 

 

 

 

While a DMA operation is in progress, -CS0 and –CS1 shall be held negated and

 

 

 

 

the width of the transfers shall be 16 bits.

 

 

 

 

If there is no hardware support for DMA mode in the host, this output signal is not

 

 

 

 

used and should not be connected at the host. In this case, the BIOS must report

 

 

 

 

that DMA mode is not supported by the host so that device drivers will not

 

 

 

 

attempt DMA mode.

 

 

 

 

A host that does not support DMA mode and implements both PCMCIA and

 

 

 

 

True-IDE modes of operation need not alter the PCMCIA mode connections

 

 

 

 

while in True-IDE mode as long as this does not prevent proper operation in any

 

 

 

 

mode.

 

 

 

 

-IORD

I

34

This signal is not used in this mode.

(PC Card Memory Mode)

 

 

 

 

-IORD

 

 

This is an I/O Read strobe generated by the host. This signal gates I/O data onto

 

 

the bus from the CompactFlash Storage Card when the card is configured to use

(PC Card I/O Mode)

 

 

 

 

the I/O interface.

 

 

 

 

-IORD

 

 

In True IDE Mode, while Ultra DMA mode is not active, this signal has the same

 

 

function as in PC Card I/O Mode.

(True IDE Mode – Except

 

 

Ultra DMA Protocol Active)

 

 

 

 

-HDMARDY

 

 

In True IDE Mode when Ultra DMA mode DMA Read is active, this signal is

(True IDE Mode – In Ultra

 

 

asserted by the host to indicate that the host is read to receive Ultra DMA data-in

DMA Protocol DMA Read)

 

 

bursts. The host may negate -HDMARDY to pause an Ultra DMA transfer.

 

 

 

 

HSTROBE

 

 

In True IDE Mode when Ultra DMA mode DMA Write is active, this signal is the

 

 

data out strobe generated by the host. Both the rising and falling edge of

(True IDE Mode – In Ultra

 

 

 

 

HSTROBE cause data to be latched by the device. The host may stop

DMA Protocol DMA Write)

 

 

 

 

generating HSTROBE edges to pause an Ultra DMA data-out burst.

 

 

 

 

 

 

 

 

 

 

Transcend Information Inc.

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Contents Placement Features Dimensions133X CompactFlash Card DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Signal Description DirGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Additional Requirements for CF Advanced Timing Modes Resistor is optional133X CompactFlash Card Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Table Typical Series Termination for Ultra DMAUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Card Configuration Multiple Function CompactFlash Storage CardsAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Feature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h OffsetSector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set LBADefinitions Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech Data Field Type InformationTS1G~32GCF133 0X00h Word 0 General Configuration Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackPIO Data Transfer Cycle Timing Mode Words 7-8 Number of Sectors per CardWords 10-19 Serial Number Word 22 ECC CountMultiple Sector Setting Total Sectors Addressable in LBA ModeMultiword DMA transfer Word 64 Advanced PIO transfer modes supportedWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 91 Advanced power management level value Word 160 Power Requirement DescriptionWord 89 Time required for Security erase unit completion Word 128 Security StatusValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supportedValue Current PIO timing mode selected Word 162 Key Management Schemes SupportedValue Current Multiword DMA timing mode selected Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported Idle 97h or E3hNOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported133X CompactFlash Card TS1G~32GCF133 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Command Set Smart Feature Register ValuesSmart Data Structure Decription
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