Transcend Information TS4GCF133, TS8GCF133, TS1GCF133, TS16GCF133, CF 133X, TS32GCF133, TS2GCF133 Gnd

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TS1G~32GCF133				133X CompactFlash Card


	Signal Name	Dir.	Pin	Description
-CE1, -CE2		I	7,32	These input signals are used both to select the card and to indicate to the card
				whether a byte or a word operation is being performed. -CE2 always accesses
(PC Card Memory Mode)				the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the
Card Enable				word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,
				-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,
				Table 31, Table 35, Table 36 and Table 37.
-CE1, -CE2				This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)
Card Enable
-CS0, -CS1				In the True IDE Mode, -CS0 is the address range select for the task file
				registers while -CS1 is used to select the Alternate Status Register and the
(True IDE Mode)
				Device Control Register.

				While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the
				width of the transfers shall be 16 bits.

-CSEL		I	39	This signal is not used for this mode, but should be connected by the host to PC
(PC Card Memory Mode)				Card A25 or grounded by the host.
-CSEL				This signal is not used for this mode, but should be connected by the host to PC
(PC Card I/O Mode)				Card A25 or grounded by the host.
-CSEL				This internally pulled up signal is used to configure this device as a Master or a
(True IDE Mode)				Slave when configured in the True IDE Mode.
				When this pin is grounded, this device is configured as a Master.
				When the pin is open, this device is configured as a Slave.

D15 - D00		I/O	31,30,29,28,	These lines carry the Data, Commands and Status information between the host
(PC Card Memory Mode)			27,49,48,47,	and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB
			6,5,4,3,2,	of the Odd Byte of the Word.
			23, 22, 21

D15 - D00				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
D15 - D00				In True IDE Mode, all Task File operations occur in byte mode on the low order
(True IDE Mode)				bus D[7:0] while all data transfers are 16 bit using D[15:0].


GND		--	1,50	Ground.
(PC Card Memory Mode)
GND				This signal is the same for all modes.
(PC Card I/O Mode)
GND				This signal is the same for all modes.
(True IDE Mode)

Transcend Information Inc.				7

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Contents Description Placement FeaturesDimensions 133X CompactFlash CardTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal DescriptionGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Resistor is optional Additional Requirements for CF Advanced Timing ModesTable Typical Series Termination for Ultra DMA 133X CompactFlash CardUltra DMA Electrical Requirements Series termination required for Ultra DMA operationUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing Specification133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Multiple Function CompactFlash Storage Cards Card ConfigurationAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh LBA CF-ATA Command SetDefinitions Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hData Field Type Information Identify Device EchTS1G~32GCF133 0X00h Word 6 Default Number of Sectors per Track Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 3 Default Number of HeadsWord 22 ECC Count PIO Data Transfer Cycle Timing ModeWords 7-8 Number of Sectors per Card Words 10-19 Serial NumberWord 64 Advanced PIO transfer modes supported Multiple Sector SettingTotal Sectors Addressable in LBA Mode Multiword DMA transferWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 89 Time required for Security erase unit completionWord 162 Key Management Schemes Supported Value Maximum PIO mode timing selectedValue Maximum Multiword DMA timing mode supported Value Current PIO timing mode selectedIdle 97h or E3h Value Current Multiword DMA timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode SupportedInitialize Drive Parameters 91h Idle Immediate 95h or E1hNOP 00h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS1G~32GCF133 Seek 7Xh Feature Supported Set Features EFh133X CompactFlash Card TS1G~32GCF133 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetDecription Smart Data Structure