Transcend Information TS1GCF133, TS4GCF133, TS8GCF133, TS16GCF133, CF 133X, TS32GCF133, TS2GCF133 Iowr

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TS1G~32GCF133

 

133X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

Dir.

Pin

Description

-IOWR

I

35

This signal is not used in this mode.

(PC Card Memory Mode)

 

 

 

 

 

 

-IOWR

 

 

The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the

(PC Card I/O Mode)

 

 

CompactFlash Storage Card controller registers when the CompactFlash

 

 

 

 

Storage Card is configured to use the I/O interface.

 

 

 

 

The clocking shall occur on the negative to positive edge of the signal (trailing

 

 

 

 

edge).

-IOWR

 

 

In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has

(True IDE Mode – Except

 

 

the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is

Ultra DMA Protocol Active)

 

 

supported, this signal must be negated before entering Ultra DMA mode

 

 

 

 

protocol.

STOP

 

 

In True IDE Mode, while Ultra DMA mode protocol is active, the assertion of this

(True IDE Mode – Ultra DMA

 

 

signal causes the termination of the Ultra DMA burst.

Protocol Active)

 

 

 

 

-OE

I

9

This is an Output Enable strobe generated by the host interface. It is used to read

(PC Card Memory Mode)

 

 

data from the CompactFlash Storage Card in Memory Mode and to read the CIS

 

 

 

 

and configuration registers.

-OE

 

 

In PC Card I/O Mode, this signal is used to read the CIS and configuration

(PC Card I/O Mode)

 

 

registers.

-ATA SEL

 

 

To enable True IDE Mode this input should be grounded by the host.

(True IDE Mode)

 

 

 

 

READY

O

37

In Memory Mode, this signal is set high when the CompactFlash Storage Card is

(PC Card Memory Mode)

 

 

ready to accept a new data transfer operation and is held low when the card is

 

 

 

 

busy.

 

 

 

 

At power up and at Reset, the READY signal is held low (busy) until the

 

 

 

 

CompactFlash Storage Card has completed its power up or reset function. No

 

 

 

 

access of any type should be made to the CompactFlash Storage Card during

 

 

 

 

this time.

 

 

 

 

Note, however, that when a card is powered up and used with RESET

 

 

 

 

continuously disconnected or asserted, the Reset function of the RESET pin is

 

 

 

 

disabled. Consequently, the continuous assertion of RESET from the application

 

 

 

 

of power shall not cause the READY signal to remain continuously in the busy

 

 

 

 

state.

-IREQ

 

 

I/O Operation – After the CompactFlash Storage Card Card has been configured

(PC Card I/O Mode)

 

 

for I/O operation, this signal is used as -Interrupt Request. This line is strobed

 

 

 

 

low to generate a pulse mode interrupt or held low for a level mode interrupt.

INTRQ

 

 

In True IDE Mode signal is the active high Interrupt Request to the host.

 

 

 

 

(True IDE Mode)

 

 

 

 

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Contents Dimensions Placement Features133X CompactFlash Card DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal DescriptionGND Inpack Iowr VCC Wait Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Resistor is optional Additional Requirements for CF Advanced Timing ModesUltra DMA Electrical Requirements 133X CompactFlash CardSeries termination required for Ultra DMA operation Table Typical Series Termination for Ultra DMAUltra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133133X CompactFlash Card Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing Specification133X CompactFlash Card TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Multiple Function CompactFlash Storage Cards Card ConfigurationAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh LBA CF-ATA Command SetDefinitions Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hData Field Type Information Identify Device EchTS1G~32GCF133 0X00h Word 1 Default Number of Cylinders Word 0 General ConfigurationWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackWords 7-8 Number of Sectors per Card PIO Data Transfer Cycle Timing ModeWords 10-19 Serial Number Word 22 ECC CountTotal Sectors Addressable in LBA Mode Multiple Sector SettingMultiword DMA transfer Word 64 Advanced PIO transfer modes supportedWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 160 Power Requirement Description Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Word 128 Security StatusValue Maximum Multiword DMA timing mode supported Value Maximum PIO mode timing selectedValue Current PIO timing mode selected Word 162 Key Management Schemes SupportedValue Maximum Pcmcia IO timing mode Supported Value Current Multiword DMA timing mode selectedValue Maximum Memory timing mode Supported Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hNOP 00h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS1G~32GCF133 Seek 7Xh Feature Supported Set Features EFh133X CompactFlash Card TS1G~32GCF133 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetDecription Smart Data Structure
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