Xilinx ML403 specifications Complete Simulation

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Simulation

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The simulation runs for 2000 ns as shown in Figure 29. There are 3 sections in the simulation, shown in the following ﬁgures.

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Figure 29: Complete Simulation

XAPP979 (v1.0) February 26, 2007

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Contents Summary Included SystemsIntroduction IntroductionIIC Primer Data Transfer on the IIC Bus Reference System Speciﬁcs Reference System SpeciﬁcsOPB IIC Registers Address ML403 XC4VFX12 Address MapOPB IIC Registers OPB IIC Control Register Bits Name DescriptionStatus Register SR Status Register Bit Deﬁnitions Contd Conﬁguring the OPB IIC Core Microchip 24LC04ML40x Schematic for IIC Connections 24LC04 Control Byte AllocationML40x Resistors Expansion Header TotalPhase Aardvark Adapter Fpga IIC PinsAardvark Control Center Executing the Reference System from EDK Software ProjectsProjects interfacing to Aardvark Adapter Project Running the ApplicationsRunning the Applications HyperTerminal Parameters Run Start → Programs → ChipScope Pro → ChipScope Inserter Using ChipScope with OPB IICInvoke XPS. Run Hardware → Generate Netlist Making Net Connections in ChipScope Inserter Start → Programs → ChipScope Pro → ChipScope Pro AnalyzerSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationSignal Name Functionality OPB IIC SimulationComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master References RevisionHistory Revision