Xilinx ML403 specifications Introduction, IIC Primer

Introduction

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Introduction

This application note accompanies a reference system built on the ML403 development board. Figure 1 is a block diagram of the reference system.

OPB	OPB UART	OPB
INTC	16550	IIC

PowerPC™

405 Processor

OPB

PLB

PLB

DDR

PLB

BRAM

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Figure 1: OPB IIC Reference System Block Diagram

The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core.

IIC Primer

Figure 2 shows components on an IIC bus.Two IIC masters and three IIC slaves are shown. The master is responsible for setting up transactions. This includes generating the clock on SCL and defining which slave is involved in the communication, with an address field, and which component is transmitting and which component is receiving. Some components are slave only, while others can transition between master and slave operation.

M1

SCL SDA

S1 S2

M2

S3

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Figure 2: IIC Bus

Figure 3 shows the START and STOP conditions. A START condition is a falling edge on SDA when SCL is high. A STOP condition is a rising edge on SDA when SCL is high. During data transfer, the data line is stable on SDA when SCL is high. Data transitions on SDA when SCL is low. Note that the START and STOP conditions are special conditions, violating the rule that data cannot transition while SCL is high.

SDA

SCL

Start Stop

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Figure 3: Start and Stop Conditions

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 2