Xilinx ML403 specifications Test code with iicAA as Master

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Simulation

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Figure 33 provides the test code used in the simulation with the OPB IIC with the AA address as the master.

write CR_20 0x40 -- GC, En

write ADR_20 0x20 - Sets address as 0x20 write CR_AA 0x01 - Enable

write ADR_AA 0xAA

write RC_FIFO_PIRQ_AA 0x0

write IER_AA 0x04 -- Enable DTRE interrupt write RC_FIFO_PIRQ 0x01 (473 us)

write DTR_20 0x3C write DTR_20 0x55

write DTR_AA 0x0 -- General Call

write CR_AA 0x0D -- RSTA, TxAK, TX, MSMS, Enable wait_for_intr

read SR_AA 0xC4 -- TFE, RFE, BB read ISR_AA 0xD4 -- TFHE, DTRE

write CR_AA 0x35 RSTA, MS, EN (547 us) write DTR_AA 0x21

write DTR_AA 0xFF write IER_AA 0x08

wait_for_intr -- waiting for DRR_AA full read SR_AA 0x0C -- SRW, BB (678 us) write CR_AA 0x37 -- Clear FIFO

write CR_AA 0x35 read DRR_AA 0x3C write ISR_AA 0xC* write DTR_AA 0x21 wait_for_intr

read SR_AA 0x8C

read ISR_AA 0xCA -- TXER, DFF Full write CR_AA 0x41

read DRR_AA 0x55 (787 us) write ISR_AA 0xC8

write IRE_AA 0x10 -- Enable Bus is not Busy wait_for_intr

X979_33_012907

Figure 33: Test code with iic_AA as Master

XAPP979 (v1.0) February 26, 2007

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Contents Summary Included SystemsIntroduction IIC PrimerIntroduction Data Transfer on the IIC Bus Reference System Speciﬁcs Reference System SpeciﬁcsOPB IIC Registers Address ML403 XC4VFX12 Address MapOPB IIC Registers OPB IIC Control Register Bits Name DescriptionStatus Register SR Status Register Bit Deﬁnitions Contd Conﬁguring the OPB IIC Core Microchip 24LC04ML40x Schematic for IIC Connections 24LC04 Control Byte AllocationML40x Resistors Expansion Header TotalPhase Aardvark Adapter Fpga IIC PinsAardvark Control Center Executing the Reference System from EDK Software ProjectsProjects interfacing to Aardvark Adapter Running the Applications Running the ApplicationsProject HyperTerminal Parameters Using ChipScope with OPB IIC Invoke XPS. Run Hardware → Generate NetlistRun Start → Programs → ChipScope Pro → ChipScope Inserter Making Net Connections in ChipScope Inserter Start → Programs → ChipScope Pro → ChipScope Pro AnalyzerSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationSignal Name Functionality OPB IIC SimulationComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master References RevisionHistory Revision