Xilinx ML403 specifications X97934012907

Page 31

Simulation

R

Figure 34 shows the third test shown in opb_iic.wlf, run from 800 - 2000 us. IIC_20 is the master writing to IIC_AA, which is a 10-bit slave.

X979_34_012907

Figure 34: Simulation with iic_AA as Master

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

31

Image 31

Contents Included Systems SummaryIIC Primer IntroductionIntroduction Data Transfer on the IIC Bus Reference System Speciﬁcs Reference System SpeciﬁcsOPB IIC Control Register Bits Name Description ML403 XC4VFX12 Address MapOPB IIC Registers OPB IIC Registers AddressStatus Register SR Status Register Bit Deﬁnitions Contd Microchip 24LC04 Conﬁguring the OPB IIC Core24LC04 Control Byte Allocation ML40x Schematic for IIC ConnectionsML40x Resistors Expansion Header Fpga IIC Pins TotalPhase Aardvark AdapterAardvark Control Center Software Projects Executing the Reference System from EDKProjects interfacing to Aardvark Adapter Running the Applications Running the ApplicationsProject HyperTerminal Parameters Invoke XPS. Run Hardware → Generate Netlist Using ChipScope with OPB IICRun Start → Programs → ChipScope Pro → ChipScope Inserter Start → Programs → ChipScope Pro → ChipScope Pro Analyzer Making Net Connections in ChipScope InserterSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationOPB IIC Simulation Signal Name FunctionalityComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master Revision RevisionHistory References