Xilinx ML403 specifications Summary, Included Systems

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Application Note: Embedded Processing

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XAPP979 (v1.0) February 26, 2007

Reference System: OPB IIC Using the ML403 Evaluation Platform

Author: Paul Glover, Ed Meinelt, Lester Sanders

Summary

This application note describes how to build a reference system for the On-Chip Peripheral Bus Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded system in the ML403 Embedded Development Platform. The reference system is Base System Builder (BSB) based.

An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly. Several software projects illustrate how to configure the OPB IIC core, set up interrupts, and do read and write operations. Some of the software projects interface the OPB IIC to the MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the TotalPhase Aardvark Adapter, which provides IIC master and slave functionality. The procedure for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a Linux kernel using MontaVista are listed. Simulation output files for analyzing basic IIC transactions are provided.

Included

Systems

Required Hardware/Tools

This application note includes one reference system:

www.xilinx.com/bvdocs/appnotes/xapp979.zip

The project name used in xapp979.zip is ml403_ppc_opb_iic.

Users must have the following tools, cables, peripherals, and licenses available and installed:

Xilinx EDK 8.2.02i

Xilinx ISE 8.2.03

Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)

Monta Vista Linux v2.4 Development Kit

Modeltech ModelSim v6.1d

ChipScope v8.2

© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

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Contents Included Systems SummaryIIC Primer IntroductionIntroduction Data Transfer on the IIC Bus Reference System Specifics Reference System SpecificsOPB IIC Registers ML403 XC4VFX12 Address MapOPB IIC Registers Address OPB IIC Control Register Bits Name DescriptionStatus Register SR Status Register Bit Definitions Contd Microchip 24LC04 Configuring the OPB IIC Core24LC04 Control Byte Allocation ML40x Schematic for IIC ConnectionsML40x Resistors Expansion Header Fpga IIC Pins TotalPhase Aardvark AdapterAardvark Control Center Software Projects Executing the Reference System from EDKProjects interfacing to Aardvark Adapter Running the Applications Running the ApplicationsProject HyperTerminal Parameters Invoke XPS. Run Hardware → Generate Netlist Using ChipScope with OPB IICRun Start → Programs → ChipScope Pro → ChipScope Inserter Start → Programs → ChipScope Pro → ChipScope Pro Analyzer Making Net Connections in ChipScope InserterSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationOPB IIC Simulation Signal Name FunctionalityComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master History RevisionReferences Revision