Siemens manual Interrupt Controller, SPC3 IRR IMR

Page 24

PROFIBUS Interface Center

SPC3

 

 

 

 

 

 

 

5.3 Interrupt Controller

The processor is informed about indication messages and various error events via the interrupt controller. Up to a total of 16 events are stored in the interrupt controller. The events are carried out on an interrupt output. The controller does not have a prioritization level and does not provide an interrupt vector (not 8259A compatible!).

The controller consists of an Interrupt Request Register (IRR), an Interrupt Mask Register (IMR), an Interrupt Register (IR), and an Interrupt Acknowledge Register (IAR).

uP uP uP SEP_INT

IR

SPC3

S

 

uP

 

IRR

IMR

 

 

R

 

IAR uP

S

FF

R

INT_Pol

X/INT uP

Each event is stored in the IRR. Individual events can be suppressed via the IMR. The input in the IRR is independent of the interrupt masks. Event signals not masked out in the IMR generate the X/INT interrupt via a sum network. The user can set each event in the IRR for debugging.

Each interrupt event the processor processed must be deleted via the IAR (except for New_Prm_Data, New_DDB_Prm_Data, and New_Cfg_Data). Log ‘1’ mustbe written on the relevant bit position. If a new event and an acknowledge from the previous event are present at the IRR at the same time, the event remains stored. If the processor subsequently enables a mask, it must be ensured that no prior input is present in the IRR. For safety purposes, the position in the IRR must be deleted prior to the mask enable.

Prior to exiting the interrupt routine, the processor must set the “end of interrupt signal (E01) = 1” in the mode register. The interrupt cable is switched to inactive with this edge change. If another event must be stored, the interrupt output is not activated again until after an interrupt inactive time of at least 1 usec or 1- 2 ms. This interrupt inactive time can be set via ‘EOI_Timebase.’ This makes it possible to again come into the interrupt routine when an edge-triggered interrupt input is used.

The polarity for the interrupt output is parameterized via the INT_Pol mode bit. After the hardware reset, the output is low-active.

 

Address

 

 

 

Bit Position

 

 

 

Designation

 

 

Control

7

6

5

4

3

2

1

0

 

 

 

Register

 

 

 

 

 

 

 

 

 

 

 

00H

Res

Res

Res

User_

WD_DP_

Baud_

Go/Leave

MAC_

Int-Req-Reg

 

 

(Intel)

 

 

 

Timer_

Mode_

rate_

Data_

Reset

7..0

 

 

 

 

 

 

Clock

Timeout

Detect

EX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

Bit Position

 

 

 

Designation

 

 

Control

15

14

13

12

11

10

9

8

 

 

 

Register

 

 

 

 

 

 

 

 

 

 

 

01H

Res

Res

DX_OUT

Diag_

New_

New_

New_

New_GC

Int-Req-Reg 7

 

 

(Intel)

 

 

 

Puffer_

Prm_

Cfg_

SSA_

Com

15..8

 

 

 

 

 

 

Changed

Data

Data

Data

mand

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 22

 

 

 

V1.3

 

 

SPC3 Hardware Description

 

2003/04

 

 

 

 

 

 

Copyright (C) Siemens AG 2003. All rights reserved.

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Contents Simatic NET Page SIM Atic NET Profibus Interface Center SPC3 Hardware DescriptionVersions Release Date ChangesMode Register Status Register Interrupt Controller Watchdog TimerDPBuffer Structure Description of the DP Services Directory11.3 Diagnostics Processing from the System View Asic TestPin Assignment Example for the RS 485 Interface SPC3 Introduction Function Overview Pin Description CmosCPD Cmos with pull down TTLt Schmitt trigger V1.3 Memory Allocation Memory Area Distribution in the SPC35FFH Segment Processor Parameters Latches/Register Significance Write Access OCH 0DH0EH 0FH Organizational Parameters RAM 1AH 1BH1CH 1DHMode Register Asic InterfaceDisstartcontrol Mode Register 1 Mode-REG1, writable STARTSPC3Exiting the Offline state EOIStatus Register Fdlindst Status Register Bit15 . .readableInterrupt Controller SPC3 IRR IMRDxout IMR IARWatchdog Timer Automatic Baud Rate IdentificationBaud Rate Monitoring Response Time MonitoringPROFIBUS-DP Interface DPBuffer StructureUart RAM Aux-Buffer ManagementDescription of the DP Services SetSlaveAddress SAP55Sequence for the SetSlaveAddress Utility SetParam SAP61 Parameter Data StructureParameter Data Processing Sequence CheckConfig SAP62 SPC3Diagnostics Processing Sequence SlaveDiagnosis SAP60SPC3 Structure of the Diagnostics Buffer WriteReadData / DataExchange DefaultSAPWriting Outputs Reading Inputs UserWatchdogTimer GlobalControl SAP58GetConfig SAP59 ReadInputs SAP56ReadOutputs SAP57 Hardware Interface Universal Processor Bus InterfaceGeneral Description Bus Interface Unit BIUXINT/MO Mode Bus Interface V1.3Switching Diagram Principles Low Cost System with 80C32System X86-Mode SPC3 Application with the 80 CApplication with th 80 C Interface Signals UartAsic Test Technical Data Maximum Limit ValuesPermitted Operating Values DC-Specifikation of the I/O- DriversAC-Specification for the Output Drivers Tabel 8.3 DC-Specifikation of the I/O- DriversCurrent Tabelle 8.5 Leakage current of the output drivers Timing Characteristics SYS Bus InterfaceClock pulse 48 Mhz Clock Pulse TimingReset Timing in the Synchronous C32-ModeST-Vers Min Max Unit TBDSynchronous Intel-Mode, Processor-Read-Timing Synchronous Intel-Mode, Processor-Write-TimingTiming in the Asynchronous Intel Mode X86 Mode ST-VersParameter Min Max Asynchronous Intel-Mode, Processor-Read-Timing XRD XCS XreadyAsynchronous Intel-Mode, Processor-Write-Timing XWR XCS4.1 74.2 Synchronous Motorola-Mode, Processor-Read-TimingSynchronous Motorola-Mode, Processor-Write-Timing Timing in the Asynchronous Motorola-Mode for example, 68HC16Asynchronous Motorola-Mode, Processor-Read-Timing XCS XdsackAsynchronous Motorola-Mode, Processor-Write-Timing Serial Bus Interface Pulse 48 MHzHousing PQFP-44 Housing SPC3 Hardware Description Symbol Min Typ Max AMI-Vers 13.6513.90 14.15Profibus Interface Pin AssignmentRTS TXDExample for the RS 485 Interface SN65ALS1176Appendix AddressesProfibus User Organisation Technical contact person at ComDeC in GermanyGeneral Definition of Terms Ordering of ASICs10.3.1 SPC3 AMI 10.3.2 SPC3 STAppendix a Diagnostics Processing in Profibus DP Diagnostics Bits and Expanded DiagnosticsIntroduction StatdiagIdentifier Byte 7 has Etc Identifier Byte 0 has Diagnostics Processing from the System View Single DiagnosticsSimatic S5 / COM ET CombiAppendix B Useful Information Data format in the Siemens PLC SimaticPage Siemens Aktiengesellschaft

SPC3 specifications

Siemens SPC3 is a state-of-the-art solution designed to enhance industrial automation, providing businesses with a robust platform for managing complex processes efficiently. This device epitomizes Siemens' commitment to innovation, blending cutting-edge technology with user-friendly features to deliver optimized performance across various applications.

One of the standout features of the Siemens SPC3 is its advanced processing capabilities. Equipped with high-performance processors, it can handle various tasks simultaneously, ensuring seamless operation even in demanding environments. This performance is complemented by enhanced memory capacity, which allows for increased data handling and improved execution speed, crucial for real-time monitoring and control applications.

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Siemens has also emphasized ease of use in the SPC3. The interface is designed to be intuitive, allowing operators to navigate and configure the system effortlessly. Coupled with comprehensive software tools, users are empowered to implement changes swiftly while minimizing downtime.

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In summary, Siemens SPC3 represents a significant advancement in industrial automation technology. Its high-performance processing, modular adaptability, advanced communication capabilities, robust security measures, and user-friendly design make it an ideal choice for businesses striving for efficiency and innovation in their operations. The SPC3 is more than just a control device; it is a comprehensive solution that meets the evolving demands of modern industries.
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