Maxim MAX12527 manual FCLK = 65.00352MHz, fIN = 175MHz, FIN = 70MHz, AIN = -0.5dBFS

Page 10

Dual, 65Msps, 12-Bit, IF/Baseband ADC

Typical Operating Characteristics (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 70MHz)

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 70MHz)

MAX12527

 

90

 

 

 

 

 

toc22

72

 

 

 

 

 

 

 

 

 

85

 

 

 

SFDR

 

MAX12527

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFDR (dBc)

80

 

 

 

 

 

SINAD(dB)

68

75

 

 

 

 

 

66

-THD,

 

 

 

-THD

 

 

SNR,

 

70

 

 

 

 

 

64

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

62

 

60

3.1

3.2

3.3

3.4

3.5

 

60

 

3.0

3.6

 

VDD (V)

SNR

toc23

MAX12527

 

 

SINAD

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

OVDD (V)

 

 

 

 

90

 

 

 

 

 

 

toc24

 

 

 

 

 

 

 

 

 

85

 

 

 

SFDR

 

 

MAX12527

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(dBc)

80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFDR

75

 

 

 

-THD

 

 

 

 

 

 

 

 

 

 

-THD,

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

 

OVDD (V)

 

 

 

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE

PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

 

72

 

 

 

 

 

 

toc25

90

 

 

 

 

 

 

 

 

 

 

70

 

 

SNR

 

 

 

MAX12527

85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(dB)

68

 

 

 

 

 

 

(dBc)

80

 

 

 

 

SINAD

 

 

 

SINAD

 

 

 

 

 

 

SFDR

 

66

 

 

 

 

 

 

75

SNR,

64

 

 

 

 

 

 

-THD,

70

 

 

 

 

 

 

 

 

 

62

 

 

 

 

 

 

 

65

 

60

 

 

 

 

 

 

 

60

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

 

 

OVDD (V)

 

 

 

 

 

 

 

 

 

 

 

toc26

900

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12527

800

 

 

 

SFDR

 

 

 

700

 

 

 

 

 

 

mA)

 

 

 

 

 

 

 

600

 

 

 

 

 

 

 

(mW,

 

 

 

 

 

 

 

500

 

 

 

 

-THD

 

 

VDD

400

 

 

 

 

 

 

, I

 

 

 

 

 

 

 

DISS

300

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

200

 

 

 

 

 

 

 

 

100

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

0

 

 

 

 

OVDD (V)

 

 

 

 

 

 

 

 

 

 

toc27

 

 

PDISS (ANALOG)

 

MAX12527

 

 

 

 

 

 

 

 

 

 

IVDD

 

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

 

80

CL 5pF

 

 

 

 

 

toc28

72

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

MAX12527

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

(mW, mA)

 

 

 

 

 

 

 

 

50

 

 

 

 

 

 

(dB)

68

PDISS (DIGITAL)

 

 

 

 

 

 

 

 

 

OVDD

40

 

 

 

 

 

 

SINAD

66

 

 

 

 

 

 

 

 

, I

30

 

 

 

 

 

 

SNR,

 

DISS

 

 

 

 

IOVDD

 

64

P

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

62

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

60

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

 

 

OVDD (V)

 

 

 

 

SNR, SINAD vs. CLOCK DUTY CYCLE

(fIN = 70MHz, AIN = -0.5dBFS)

SNR

toc29

MAX12527

 

SINAD

 

SINGLE-ENDED CLOCK INPUT DRIVE

25

35

45

55

65

75

 

 

CLOCK DUTY CYCLE (%)

 

 

-THD, SFDR vs. CLOCK DUTY CYCLE

(fIN = 70MHz, AIN = -0.5dBFS)

 

90

 

toc30

 

 

SFDR

 

 

MAX12527

 

85

 

 

 

 

(dBc)

80

 

 

 

-THD

 

SFDR

 

 

75

 

 

-THD,

70

 

 

 

 

 

 

65

 

 

SINGLE-ENDED CLOCK INPUT DRIVE

60

25

35

45

55

65

75

 

 

CLOCK DUTY CYCLE (%)

 

 

10 ______________________________________________________________________________________

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Contents Applications FeaturesGeneral Description Ordering InformationAnalog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Parameter Symbol Conditions MIN TYPClock Inputs CLKP, Clkn Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVOvdd Power RequirementsD0A-D11A, Dora DIFFCLK/SECLK = GNDFFT Plot 16,384-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS PIN Name Function Pin DescriptionSame side of the PC board D2B D0BD1B D3BRefout Detailed DescriptionShref RefinFunctional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesSystem Timing Requirements DIV4 DIV2 FunctionDOR Equivalent BinaryD11A-D0A D11A-D0A D11B-D0B CODE10Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12527Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching Package Information 68L QFN THIN.EPS