Maxim MAX12527 manual Applications Information, Using Transformer Coupling

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Dual, 65Msps, 12-Bit, IF/Baseband ADC

MAX12527

Applications Information

Using Transformer Coupling

In general, the MAX12527 provides better SFDR and THD with fully differential input signals than single- ended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode.

An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12527 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the

 

 

 

24.9Ω

 

 

 

IN_P

 

 

 

5.6pF

 

0.1µF

 

MAX12527

VIN

1

6

T1

 

 

 

5

2

COM_

 

N.C.

 

 

3

4

0.1µF

 

 

 

MINICIRCUITS

 

 

TT1-6

 

 

 

OR

 

24.9Ω

 

T1-1T

 

IN_N

 

 

 

5.6pF

overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (fCLK / 2).

The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75Ω and 113Ω termination resistors provide an equivalent 50Ω termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0Ω resistors in series with the analog inputs allow high IF input fre- quencies. These 0Ω resistors can be replaced with low- value resistors to limit the input bandwidth.

Single-Ended AC-Coupled Input Signal

Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.

VIN

0.1µF

0Ω

 

 

 

MAX4108

 

IN_P

 

5.6pF

 

 

100Ω

 

24.9Ω

 

 

MAX12527

 

 

COM_

 

 

0.1µF

100Ω

 

24.9Ω

 

 

IN_N

 

 

5.6pF

Figure 9. Transformer-Coupled Input Drive for Input Frequencies

Figure 11. Single-Ended, AC-Coupled Input Drive

Up to Nyquist

 

 

 

 

 

 

 

 

0Ω*

 

0.1µF

 

 

 

 

 

5.6pF

 

1

6

 

1

6

 

VIN

75Ω

 

113Ω

T1

 

T2

 

 

 

 

 

1%

 

 

 

0.5%

 

5

2

N.C.

5

2

N.C.

 

 

N.C.

 

N.C.

 

 

 

 

 

75Ω

 

 

 

0.1µF

 

3

4

3

4

 

113Ω

 

MINICIRCUITS

1%

MINICIRCUITS

 

0.5%

 

 

 

0Ω*

 

ADT1-1WT

 

ADT1-1WT

 

 

 

 

 

 

 

 

*0Ω RESISTORS CAN BE REPLACED WITH

5.6pF

 

 

 

 

LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.

IN_P

MAX12527

COM_

IN_N

Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist

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Contents Applications FeaturesGeneral Description Ordering InformationAnalog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Parameter Symbol Conditions MIN TYPClock Inputs CLKP, Clkn Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVOvdd Power RequirementsD0A-D11A, Dora DIFFCLK/SECLK = GNDFFT Plot 16,384-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS PIN Name Function Pin DescriptionSame side of the PC board D2B D0BD1B D3BRefout Detailed DescriptionShref RefinFunctional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesSystem Timing Requirements DIV4 DIV2 Function DOR Equivalent Binary D11A-D0A D11A-D0A D11B-D0B CODE10Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12527Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching Package Information 68L QFN THIN.EPS