Maxim MAX12527 manual Buffered External Reference Drives Multiple ADCs

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Dual, 65Msps, 12-Bit, IF/Baseband ADC

3.3V

0.1µF2.2µF

MAX12527

0.1µF1

5

MAX6029

(EUK21)

2

16.2kΩ

1µF

3

4

									0.1µF	2.048V
5									0.1µF	300µF
									47Ω




			1							6V

MAX4230

2

1.47kΩ

VDD

REFINREF_P

MAX12527

REF_N

REFOUTCOM_

0.1µF

10µF		0.1µF

0.1µF

0.1µF

GND

0.1µF

NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT.

3.3V

0.1µF2.2µF

0.1µF

VDD

REFINREF_P

MAX12527

REF_N

REFOUTCOM_

GND

0.1µF

10µF		0.1µF

0.1µF

0.1µF

Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference

Buffered External Reference Drives Multiple ADCs

The buffered external reference mode allows for more control over the MAX12527 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ.

Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple con- verters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230.

The MAX4230 buffers the 2.048V reference and pro- vides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12527.

Unbuffered External Reference Drives Multiple ADCs

The unbuffered external reference mode allows for pre- cise control over the MAX12527 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal refer-

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Contents Ordering Information FeaturesGeneral Description ApplicationsConversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, InbnParameter Symbol Conditions MIN TYP MAX Units Vcom Interchannel CharacteristicsInternal Reference Refout Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAV Parameter Symbol Conditions MIN TYPClock Inputs CLKP, Clkn Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4DIFFCLK/SECLK = GND Power RequirementsD0A-D11A, Dora OvddFFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure FFT Plot 16,384-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzFIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS Same side of the PC board Pin DescriptionPIN Name Function D3B D0BD1B D2BRefin Detailed DescriptionShref RefoutFunctional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H AmplifierClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsD11A-D0A D11B-D0B CODE10 Equivalent BinaryD11A-D0A DOR Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer CouplingSingle-Ended AC-Coupled Input Signal Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12527 Grounding, Bypassing, and Board LayoutParameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery TimeOffset Matching Pin ConfigurationGain Matching 68L QFN THIN.EPS Package Information