Maxim MAX12527 manual Parameter Symbol Conditions MIN TYP, Clock Inputs CLKP, Clkn

Page 5

Dual, 65Msps, 12-Bit, IF/Baseband ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -0.5dBFS (differen- tial), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40°C to

+85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

 

SYMBOL

 

CONDITIONS

 

MIN

TYP

MAX

 

UNITS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REF_P Sink Current

 

IREFAP

 

VREF_P = 2.418V

 

 

1.2

 

 

mA

 

IREFBP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REF_N Source Current

 

IREFAN

 

VREF_N = 0.882V

 

 

0.85

 

 

mA

 

IREFBN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COM_ Sink Current

 

ICOMA

 

VCOM_ = 1.65V

 

 

0.85

 

 

mA

 

ICOMB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REF_P, REF_N Capacitance

 

CREF_P,

 

 

 

 

13

 

 

pF

 

CREF_N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COM_ Capacitance

 

CCOM_

 

 

 

 

6

 

 

pF

CLOCK INPUTS (CLKP, CLKN)

 

 

 

 

 

 

 

 

 

 

Single-Ended Input High

 

VIH

 

DIFFCLK/SECLK = GND, CLKN = GND

 

0.8 x

 

 

 

V

Threshold

 

 

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

Single-Ended Input Low

 

VIL

 

DIFFCLK/SECLK = GND, CLKN = GND

 

 

 

0.2 x

 

V

Threshold

 

 

 

 

 

VDD

 

 

 

 

 

 

 

 

 

 

Minimum Differential Clock Input

 

 

 

DIFFCLK/SECLK = OVDD

 

 

0.2

 

 

VP-P

Voltage Swing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Differential Input Common-Mode

 

 

 

DIFFCLK/SECLK = OVDD

 

 

VDD / 2

 

 

V

Voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_ Input Resistance

 

RCLK

 

Each input (Figure 4)

 

 

5

 

 

kΩ

CLK_ Input Capacitance

 

CCLK

 

Each input

 

 

2

 

 

pF

DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input High Threshold

 

VIH

 

 

 

0.8 x

 

 

 

V

 

 

 

 

OVDD

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Low Threshold

 

VIL

 

 

 

 

 

0.2 x

 

V

 

 

 

 

 

 

OVDD

 

 

 

 

 

 

 

 

 

 

 

Input Leakage Current

 

 

 

OVDD applied to input

 

 

 

±5

 

µA

 

 

 

Input connected to ground

 

 

 

±5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Digital Input Capacitance

 

CDIN

 

 

 

 

5

 

 

pF

DIGITAL OUTPUTS (D0A–D11A, D0B–D11B, DORA, DORB, DAV)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0A–D11A, D0B–D11B, DORA, DORB:

 

 

 

0.2

 

 

Output-Voltage Low

 

VOL

 

ISINK = 200µA

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

DAV: ISINK = 600µA

 

 

 

0.2

 

 

 

 

 

 

D0A–D11A, D0B–D11B, DORA, DORB:

 

OVDD -

 

 

 

 

Output-Voltage High

 

VOH

 

ISOURCE = 200µA

 

0.2

 

 

 

V

 

 

DAV: ISOURCE = 600µA

 

OVDD -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tri-State Leakage Current

 

ILEAK

 

OVDD applied to input

 

 

 

±5

 

µA

(Note 4)

 

 

Input connected to ground

 

 

 

±5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12527

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Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Vcom Interchannel CharacteristicsInternal Reference Refout Clock Inputs CLKP, Clkn Parameter Symbol Conditions MIN TYPDigital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVD0A-D11A, Dora Power RequirementsOvdd DIFFCLK/SECLK = GNDTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 16,384-POINT Data Record FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzFIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS Same side of the PC board Pin DescriptionPIN Name Function D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsD11A-D0A Equivalent BinaryDOR D11A-D0A D11B-D0B CODE10Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer CouplingSingle-Ended AC-Coupled Input Signal Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12527 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDOffset Matching Pin ConfigurationGain Matching 68L QFN THIN.EPS Package Information