Maxim MAX12527 manual Parameter Definitions

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Dual, 65Msps, 12-Bit, IF/Baseband ADC

mount devices for minimum inductance. Bypass VDD to GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. Bypass OVDD to GND with a 220µF ceramic capacitor in parallel with at least one 10µF, one 4.7µF, and one 0.1µF ceramic capacitor. High-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins.

Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All grounds and the exposed backside paddle of the MAX12527 must be connected to the same ground plane. The MAX12527 relies on the exposed backside paddle con- nection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground.

Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns.

Ensure that the differential, analog input network layout is symmetric and that all parasitic components are bal- anced equally. Refer to the MAX12557 EV kit data sheet for an example of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer function from a straight line. For the MAX12527, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nulli- fied. INL deviations are measured at every step of the transfer function and the worst-case deviation is report- ed in the Electrical Characteristics table.

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12527, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the midscale MAX12527 transition occurs at 0.5 LSB above mid- scale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual trans- fer function is measured between two data points: posi- tive full scale and negative full scale. Ideally, the positive full-scale MAX12527 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.

Small-Signal Noise Floor (SSNF)

SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an ampli- tude of -35dBFS. This parameter captures the thermal and quantization noise characteristics of the data con- verter and can be used to help calculate the overall noise figure of a digital receiver signal path.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the ADC’s reso- lution (N bits):

SNR[max] = 6.02 × N + 1.76

In reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spec- tral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 through HD7), and the DC offset.

SNR = 20 x log (SIGNALRMS / NOISERMS)

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig- nal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.

MAX12527

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Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom Clock Inputs CLKP, Clkn Parameter Symbol Conditions MIN TYPDigital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVD0A-D11A, Dora Power RequirementsOvdd DIFFCLK/SECLK = GNDTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 16,384-POINT Data Record FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS PIN Name Function Pin DescriptionSame side of the PC board D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsD11A-D0A Equivalent BinaryDOR D11A-D0A D11B-D0B CODE10Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12527 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching 68L QFN THIN.EPS Package Information