Maxim MAX12527 manual Package Information, 68L QFN THIN.EPS

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MAX12527

Dual, 65Msps, 12-Bit, IF/Baseband ADC

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

			68L QFN THIN.EPS
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142	C	1	2

PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
21-0142	C	2	2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.

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Contents Features General DescriptionApplications Ordering InformationParameter Symbol Conditions MIN TYP MAX Units DC Accuracy Dynamic Characteristics differential inputsAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom Parameter Symbol Conditions MIN TYP Clock Inputs CLKP, ClknDigital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVPower Requirements D0A-D11A, DoraOvdd DIFFCLK/SECLK = GNDTypical Operating Characteristics Timing Characteristics FigureFFT Plot 16,384-POINT Data Record FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS PIN Name Function Pin DescriptionSame side of the PC board D0B D1BD2B D3BDetailed Description ShrefRefout RefinFunctional Diagram Reference Configurations Reference ModeAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesSystem Timing Requirements DIV4 DIV2 FunctionEquivalent Binary D11A-D0ADOR D11A-D0A D11B-D0B CODE10Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12527Parameter Definitions Aperture Delay Full-Power BandwidthOverdrive Recovery Time Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching Package Information 68L QFN THIN.EPS