Maxim MAX12527 manual THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS

Page 9

Dual, 65Msps, 12-Bit, IF/Baseband ADC

Typical Operating Characteristics (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

-THD, SFDR vs. ANALOG INPUT AMPLITUDE

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

SNR, SINAD vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)

 

75

 

toc13

 

95

 

 

 

 

 

 

SNR

 

MAX12527

 

85

 

65

 

 

 

 

 

 

(dB)

55

 

 

(dBc)

75

 

 

 

 

 

 

65

SINAD

 

 

 

SFDR

45

 

 

55

SNR,

SINAD

 

 

-THD,

 

 

 

35

 

 

 

 

 

 

 

45

 

 

 

 

 

 

25

 

 

 

35

 

 

 

 

 

 

15

 

 

 

25

 

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10

-5

0

 

 

 

 

toc14

72

 

 

 

SFDR

 

MAX12527

70

 

 

 

 

 

 

 

SINAD (dB)

68

 

 

66

-THD

 

SNR,

 

 

 

64

 

 

 

 

 

 

62

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10

-5

0

60

 

SNR

toc15

MAX12527

 

SINAD

 

20

25

30

 

35

 

40

45

50

55

60

65

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12527

AIN (dBFS)

AIN (dBFS)

fCLK (MHz)

-THD, SFDR vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)

 

90

 

 

SFDR

 

 

 

 

toc16

72

 

 

 

 

 

 

 

 

 

 

85

 

 

 

 

 

 

 

 

MAX12527

70

 

 

 

 

 

 

 

 

 

 

 

SFDR (dBc)

80

 

 

-THD

 

 

 

 

 

SINAD(dB)

68

 

 

 

 

 

 

 

 

75

 

 

 

 

 

 

 

 

66

-THD,

70

 

 

 

 

 

 

 

 

SNR,

64

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

62

 

60

 

 

 

 

 

 

 

 

 

60

 

20

25

30

35

40

45

50

55

60

65

 

 

 

 

 

 

fCLK (MHz)

 

 

 

 

 

SNR, SINAD vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)

 

toc17

SNR

MAX12527

 

 

SINAD

20

25

30

35

40

45

50

55

60

65

 

 

 

 

fCLK (MHz)

 

 

 

 

-THD, SFDR vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)

 

90

 

 

 

 

 

 

 

 

toc18

 

 

 

 

 

 

 

 

 

 

 

85

 

 

SFDR

 

 

 

 

 

MAX12527

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFDR (dBc)

80

 

 

 

 

 

 

 

 

 

75

 

 

-THD

 

 

 

 

 

 

-THD,

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

 

 

20

25

30

35

40

45

50

55

60

65

 

 

 

 

fCLK (MHz)

 

 

 

 

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 70MHz)

(fCLK = 65.00352MHz, fIN = 70MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

 

72

 

 

SNR

 

 

toc19

90

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12527

 

 

70

 

 

 

 

 

85

 

 

 

 

 

 

 

 

SINAD(dB)

68

 

SINAD

 

 

SFDR (dBc)

80

 

 

 

 

 

66

 

 

 

 

 

75

SNR,

64

 

 

 

 

 

-THD,

70

 

 

 

 

 

 

 

 

62

 

 

 

 

 

 

65

 

60

 

 

 

 

 

 

60

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

 

 

 

 

 

 

 

toc20

72

 

 

 

SFDR

 

 

 

 

 

 

 

 

MAX12527

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

 

 

 

(dB)

68

 

 

 

 

 

-THD

 

 

 

 

 

 

SINAD

 

 

 

 

 

 

 

66

 

 

 

 

 

 

SNR,

64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

3.0

3.1

3.2

3.3

3.4

3.5

3.6

60

 

 

 

 

SNR

 

 

toc21

 

 

 

 

 

MAX12527

 

 

 

 

 

 

 

 

SINAD

 

 

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

VDD (V)

VDD (V)

_______________________________________________________________________________________ 9

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Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Clock Inputs CLKP, Clkn Parameter Symbol Conditions MIN TYPDigital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Digital Outputs D0A-D11A, D0B-D11B, DORA, DORB, DAVD0A-D11A, Dora Power RequirementsOvdd DIFFCLK/SECLK = GNDTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 16,384-POINT Data Record FFT Plot 32,768-POINT Data RecordMAX12527 THD, Sfdr vs. Clock Speed fIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHz FIN = 70MHz, AIN = -0.5dBFSTHD, Sfdr vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS SNR, Sinad vs. Temperature fIN = 175MHz, AIN = -0.5dBFS Pin Description PIN Name FunctionSame side of the PC board D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsD11A-D0A Equivalent BinaryDOR D11A-D0A D11B-D0B CODE10Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12527 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDPin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information