BenQ PE8700 service manual Procedure Pbpr Offset adjustment AD PB, PR Offset

Page 34

Filter

1

Contrast

76

 

 

 

 

Color Temp

2

Saturation

49

 

 

Pb offset

60

 

 

 

 

 

 

Pr offset

60

 

 

 

 

Procedure:

(a). PBPR Offset adjustment: (AD PB, PR Offset)

1. The variance of color coordinate via Pb offset and Pr offset:

 

x

y

Pb offset

x

y

Pb offset

x

y

Pr offset

x

y

Pr offset

x

y

If we line the x and y, then the Pb offset is the shift action and the Pr offset is the rotational action.

2.Connect power, YPbPr Video into projector.

3.Change Timing and pattern of pattern generator : Timing : 480P(H:31.54 KHz,V:60.08 Hz) pattern : 10gray Pattern

4.Turn on projector

5.Set user OSD values to default.

6.Enter factory mode.

7.Set Factory values to default.

8.Follow the Pb, Pr offset adjustment flow chart to adjust color temperature to 6500K

b). Gray Level: (AD YPBPR Contrast, Brightness)

1.

 

Change Timing and pattern of pattern generator :

 

 

Timing : 480P(H:31.54 KHz,V:60.08 Hz)

 

 

 

 

 

 

pattern : gray 32( or gray16 only for overscan)

2.

 

Adjust the Brightness of AD9883 (RGB) to let the black level of the gray

 

32 to just distinguish. Use Lux meter to measure the white level of the gray 32. Adjust

 

the contrast value of AD9883 (RGB) to let the light output to just max.

3.

Check the 32 levels of gray. All steps must appear,

33

Image 34
Contents DLP Projector Contents Safety Precautions Servicing PrecautionsEngineering Specification MinimumPage Hdtv IEC Vcci Appendix a Optical Measurement ContentGeneral requirements Practical consideration A1. BrightnessA2. Brightness Uniformity A5. Peak Contrast A9. Zoom Ratio Purpose Appendix B Design Verification Test ProcedureTest Summary Definition Test OrderAppendix C Drawings and Attachments Page Appendix D HD2 Front Projection Image Quality Specification White test screen Gray 6 test screenGray 10 test screen Black test screenTest Conditions as tested in OEM projector Red Ramp test screen· Refer to for acceptance criteria, in specified order Image Quality Specification Support Timings by DVI-I Input Analog or Digital PC signals Appendix E Supporting TimingsPage Spare Parts List Projector PE8700 99.J5877.B21Black Diagram BNCPackaging Description Appearance Description Page OSD Default value used for color delay alignment Alignment ProcedureProcedure EquipmentSelect Save Setting at Factory OSDFactory OSD Default value used for DVI-Analog color alignment White Level Adjustment AD contrast---R,G,B gain Procedure Black Level Adjustment DLP brightnessOffset adjustment at low brightness AD R, G, B offset OSD Default value used for Ypbpr color alignment User setupwhite C15400k C26500k C37500kYPbPr Component Equipment Procedure Pbpr Offset adjustment AD PB, PR Offset Gray Level AD Ypbpr Contrast, BrightnessSaturation Level Scalar Case x1x0 & y1 y0 User setupwhite C15700k C26500k C39300k Factory SDGray Level for Ycbcr Component Procedure Saturation LevelGray Level for Composite Video & S-Video Equipment OSD Default value Value USERPictureProcedure Gray Level Additional Patterns used for color final checkTrouble Shooting Guide System trouble shootingMain board trouble shooting YESSIL504 trouble shooting U4, U2 CPU U10 trouble shooting guide DMD board trouble shooting guide YESConnector board trouble shooting guide OK?Power board trouble shooting guide 鐐 衒 蘠 耟  鞤 矏 矏 耟 礼袨 蘠 醥 袓 藜 耟  韗 齇 耟  斉 鞥 觖 罿 蘠 韘 篧 蚴 礼  誜 袨 鷘 矏 篧 袨 ゾ 篧 礼 榢 譗 む 鞥 觖蛂 豽 袕 む 醥 藜 罿袨 矏 篧 ソ 譂 Factory OSD Operation FactoryHD Adj STD AdjColor Balance Filter Bypass DLP Pattern1Pattern2 Pattern3Test Mode Firmware Upgrade Procedure Page 12. RS232 Codes Page X00 Must be Reversed , no function X57 Picture by picture display Page Following is the list of Y-group Page ACK = Y1Y Page Page Page Openable Dvdoreset DeintdoneMcureset Mcureset TriggerBenq Corporation DIIN7 DIIN8DIIN9 DIIN6 DIIN4CLK54 22DETECT ResetdvdoInterlacedetect 32DETECTBenq Corporation MEMDQ14 WIRETP30 RM1OP EnableRM1CLKIN WIRETP31 CP UD0 CP UD1Resetvcc CPUA8 Resetn SDA SCLResetvcc Powerontest CP UD0 CPUS2 Resetn CPUA3 CpurdnWIRETP51 INLTCH26 WIRETP53WIRETP52 INLTCH25 WIRETP46 INLTCH27This PIN only for Test MEMDQ30 MEMDQ1 MEMDQ31 MEMDQ0MEMDQ15 MEMDQ48 MEMDQ14 MEMDQ49Cwindex Circuit FLADDR12 FLADDR16U2C CTM1M CTMN1MScrew Holes P2P5VINDDAN10 DDAN11 DDAN12 DDAN13 DDAN14 DDAN15 ScrlrDAD1000 SSI Color Wheel Drive Circuit Benq Corporation 500 OHM Vsync CAP 1CAPP+Capp HSB BnchsVoltage level of CB/CR is Sogout Vsout ADR0Datack Hsout AdrinCR1IN CB 1IN Sogy Sogyin Sogrca Racin ResetScin Inta1TURN on Larry Lin1 RESETR111 Hsdjtr R101 ResetzdviResetzdvi RES Oclk INV Dviscl DVISCL3V Dvisda DVISDA3V
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