Transcend Information 400X Input Power Input Characteristics for Udma mode, Parameter Symbol

Page 17

TS16G~64GCF400		400X CompactFlash Card

Input Power

Input Characteristics for UDMA mode >4

In UDMA modes greater than 4, the following characteristics apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.

Table: Input Characteristics (UDMA Mode > 4)
Parameter	Symbol		MIN	MAX	Units
DC supply voltage to drivers	VDD3		3.3 –8%	3.3% + 8%	Volts
Low to high input threshold	V+		1.5	2.0	Volts
High to low input threshold	V-		1.0	1.5	Volts
Difference between input thresholds:	VHYS		320		Volts
((V+ current value) - (V-current value))	VHYS		320		Volts
((V+ current value) - (V-current value))
Average of thresholds:	VTHRAVG		1.3	1.7	Volts
((V+ current value) + (V-current value))/2	VTHRAVG		1.3	1.7	Volts
((V+ current value) + (V-current value))/2

Output Drive Characteristics for UDMA mode > 4

In UDMA modes greater than 4, the characteristics specified in the following table apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.

Table: Output Drive Characteristics (UDMA Mode > 4)

	Parameter	Symbol	MIN
	DC supply voltage to drivers	VDD3	3.3 –8%
	Voltage output high at -6 mA to +3 mA (at VoH2 the output shall	VoH2	VDD3–0.51
	be able to supply and sink current toVDD3)	VoH2	VDD3–0.51
	be able to supply and sink current toVDD3)
	Voltage output low at 6 mA	VoL2

MAX

3.3% + 8%

VDD3+0.3

0.51

Units

Volts

Volts

Volts

Notes:
1)	IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity.
2)	IoH value at 400 A is insufficient in the case of DMARQ that is pulled low by a 5.6 k resistor.
3)		μ		Ω
	Voltage output high and low values shall be met at the source connector to include the effect of series termination.
4) A device shall have less than 64			A of leakage current into a 6.2 K pull-down resistor while the INTRQ signal is in the released
	state.		Ω
μ
Transcend Information Inc.			17
				V1.0

Image 17

Contents Description Placement FeaturesDimensions Specification Actual Capacity PerformanceModel P/N Model P/N User LBA Cylinder Head SectorBlock Diagram TS16G~64GCF400 True IDE Mode4 PC Card Memory Mode PC Card I/O ModePin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Output Drive Type Input CharacteristicsInput Leakage Current Type Parameter Symbol Conditions Output Drive CharacteristicsOutput Drive Characteristics Signal Name Dir Pin Description Signal Description400X CompactFlash Card StschgGND CselPin Description Signal NameDir Intrq StopReady Dmack Reset REG Iordy WaitDdmardy DstrobeCompactFlash Interface I/O at Electrical SpecificationParameter Symbol Input Power Input Characteristics for Udma modeOutput Drive Characteristics for Udma mode UnitsSignal Card10 Host10 Signal InterfacePull-up pin 45 BVD2 to avoid sensing their batteries as Low LowLow state 150 a high state per socketTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Symbol Attribute Memory Read Timing SpecificationIeee Symbol Min ns Max ns Speed VersionSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write TimingCycle Time Mode Common Memory Read Timing SpecificationIeee 250 ns 120 ns 100 ns 80 ns MinCycle Time Mode 250 ns Symbol Common Memory Write Timing SpecificationSymbol 120 ns Min 100 ns MinMin Max Symbol Input Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns TsuHIOW TDVIWH ThHIOW TlWHDX TwHIOW TlWLIWH Output Write Timing SpecificationCycle Time Mode 255 ns 120 ns 100 ns 80 ns T6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS16G~64GCF400 True IDE Multiword DMA Mode Read/Write Timing Specification True IDE Ultra DMA Mode Read/Write Timing Specification Udma Signal Type PC Card MEM PC Card IO Mode True IDE ModeMode Udma Pin # NonTS16G~64GCF400 Name Name Comment Udma Name Mode Mode4Min Max 14.7Falling Edge Slew Rate for any signal Rising Edge Slew Rate for any signalMultiple Function CompactFlash Storage Cards Card ConfigurationREG Selected SpaceDMA Stop Dmardy Strobe Dmarq Dmack HioeHIO Inpack REGAttribute Memory Function Function ModeTable Attribute Memory Function DMA CMD REGConfiguration Option Register Base + 00h in Attribute Memory TS16G~64GCF400 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionDMA REG Hioe HiowDmardy Strobe Table PC Card I/O Mode Udma FunctionDmarq Dmack Stop Hioe Wait DMA A10 Inpack REG HiowCE2 CE1 D15-D8 D7-D0 Common Memory Transfer FunctionTable Common Memory Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS16G~64GCF400 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Execute Drive Diagnostic 90h Check Power Mode 98h or E5hBit Command Cyl High Cyl Low Sec Num Sec Cnt FeatureErase Sectors C0h Transcend Information IncFlush Cache E7h Format Track 50hWord Default Total Data Field Type Information Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureIdentify Device Ech BytesDefault Total Data Field Type Information Word 1 Default Number of Cylinders Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting 164 162 0000h Key management schemes supported 163Word 6 Default Number of Sectors per Track Word 3 Default Number of HeadsWord 49 Capabilities Bit 13 Standby Timer PIO Data Transfer Cycle Timing ModeTotal Sectors Addressable in LBA Mode Multiple Sector SettingCurrent Capacity Multiword DMA transferWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 160 Power Requirement Description Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Word 128 Security Status Bit 8 Security LevelMaximum PIO mode timing selected Value Current PIO timing mode selectedMaximum Multiword DMA timing mode supported Additional Requirements for CF Advanced Timing ModesMaximum Memory timing mode Supported Value Current Multiword DMA timing mode selectedMaximum Pcmcia IO timing mode Supported Value PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Idle Immediate 95h or E1h Idle 97h or E3hInitialize Drive Parameters 91h NOP 00hRead DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS16G~64GCF400 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS16G~64GCF400 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS16G~64GCF400 TS16G~64GCF400 Error Register Status Register Error PostingNOP BBKBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Smart Command Set Smart Feature Register Values Smart Command SetSmart Data Structure DescriptionSMI CompactFlash Card Ordering InformationTranscend Product Capacity