Transcend Information TS16G-64GCF400, 400X Card Drive Address Register Address 3F7h377h Offset Fh

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TS16G~64GCF400		400X CompactFlash Card

Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh)

This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7.

Bit 7: this bit is unknown.

Implementation Note:

Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the PCMCIA implementation:

1)Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses.

2)Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.

3)Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.

4)Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software shall not attempt to use information in the Drive Address Register.

Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1.

Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.

Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.

Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.

Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.

Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.

Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.

Transcend Information Inc.

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Contents Dimensions Placement FeaturesDescription Specification Model P/N PerformanceActual Capacity Model P/N User LBA Cylinder Head SectorBlock Diagram TS16G~64GCF400 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O ModeTrue IDE Mode4 PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Input Leakage Current Input CharacteristicsOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsType Parameter Symbol Conditions 400X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description StschgCsel GNDDir Signal NamePin Description Ready StopIntrq REG ResetDmack Ddmardy WaitIordy DstrobeElectrical Specification CompactFlash Interface I/O atOutput Drive Characteristics for Udma mode Input Power Input Characteristics for Udma modeParameter Symbol UnitsSignal Interface Signal Card10 Host10Low state LowPull-up pin 45 BVD2 to avoid sensing their batteries as Low 150 a high state per socketSeries termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSymbol Speed VersionTable Configuration Register Attribute Memory Write Timing Speed Version 250 ns Symbol Min ns Max nsIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns MinSymbol 120 ns Min Common Memory Write Timing SpecificationCycle Time Mode 250 ns Symbol 100 ns MinCycle Time Mode 250 ns 120 ns 100 ns 80 ns Input Read Timing SpecificationMin Max Symbol Cycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationTsuHIOW TDVIWH ThHIOW TlWHDX TwHIOW TlWLIWH Mode True IDE PIO Mode Read/Write Timing SpecificationT6Z TS16G~64GCF400 True IDE Multiword DMA Mode Read/Write Timing Specification True IDE Ultra DMA Mode Read/Write Timing Specification Mode Udma PC Card MEM PC Card IO Mode True IDE ModeUdma Signal Type Pin # NonTS16G~64GCF400 Name Name Comment Min Max Name Mode Mode4Udma 14.7Rising Edge Slew Rate for any signal Falling Edge Slew Rate for any signalREG Card ConfigurationMultiple Function CompactFlash Storage Cards Selected SpaceHIO Stop Dmardy Strobe Dmarq Dmack HioeDMA Inpack REGTable Attribute Memory Function Function ModeAttribute Memory Function DMA CMD REGConfiguration Option Register Base + 00h in Attribute Memory TS16G~64GCF400 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory DMA REG Table Pcmcia Mode I/O FunctionTransfer Function Hioe HiowDmarq Dmack Stop Hioe Wait DMA A10 Table PC Card I/O Mode Udma FunctionDmardy Strobe Inpack REG HiowTable Common Memory Function Common Memory Transfer FunctionCE2 CE1 D15-D8 D7-D0 True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9 Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write Only Sector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS16G~64GCF400 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Command CodeDefinitions Bit Command Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Cyl High Cyl Low Sec Num Sec Cnt FeatureFlush Cache E7h Transcend Information IncErase Sectors C0h Format Track 50hIdentify Device Ech Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information BytesDefault Total Data Field Type Information CF Advanced True IDE Timing Mode Capability and Setting 164 Word 0 General ConfigurationWord 1 Default Number of Cylinders 162 0000h Key management schemes supported 163Word 49 Capabilities Bit 13 Standby Timer Word 3 Default Number of HeadsWord 6 Default Number of Sectors per Track PIO Data Transfer Cycle Timing ModeCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Multiword DMA transferWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security Status Bit 8 Security LevelMaximum Multiword DMA timing mode supported Value Current PIO timing mode selectedMaximum PIO mode timing selected Additional Requirements for CF Advanced Timing ModesMaximum Pcmcia IO timing mode Supported Value Current Multiword DMA timing mode selectedMaximum Memory timing mode Supported Value Maximum PC Card Memory Udma timing mode Supported Value Maximum PC Card I/O Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Initialize Drive Parameters 91h Idle 97h or E3hIdle Immediate 95h or E1h NOP 00hRead Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS16G~64GCF400 Seek 7Xh Set Features EFh Request Sense 03hFeature Supported TS16G~64GCF400 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS16G~64GCF400 TS16G~64GCF400 NOP Error PostingError Register Status Register BBKBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Smart Data Structure Smart Command SetSmart Command Set Smart Feature Register Values DescriptionSMI Transcend Product Capacity Ordering InformationCompactFlash Card