Transcend Information TS16G-64GCF400, 400X dimensions Reg, Dmack, Reset

Page 14

TS16G~64GCF400

 

400X CompactFlash Card

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

Dir.

Pin

Description

-REG

I

44

This signal is used during Memory Cycles to distinguish between Common

Memory and Register (Attribute) Memory accesses. High for Common Memory,

(PC Card Memory Mode– Except

 

 

 

 

Low for Attribute Memory.

Ultra DMA Protocol Active)

 

 

 

 

 

 

Attribute Memory Select

 

 

In PC Card Memory Mode, when Ultra DMA Protocol is supported by the host

 

 

 

 

and the host has enabled Ultra DMA protocol on the card the, host shall keep the

 

 

 

 

-REG signal negated during the execution of any DMA Command by the device.

-REG

 

 

The signal shall also be active (low) during I/O Cycles when the I/O address is on

(PC Card I/O Mode –Except Ultra

 

 

the Bus.

DMA Protocol Active)

 

 

In PC Card I/O Mode, when Ultra DMA Protocol is supported by the host and the

 

 

 

 

 

 

 

 

host has enabled Ultra DMA protocol on the card the, host shall keep the -REG

 

 

 

 

signal asserted during the execution of any DMA Command by the device.

-DMACK

 

 

This is a DMA Acknowledge signal that is asserted by the host in response to

(PC Card Memory Mode when

 

 

(-)DMARQ to initiate DMA transfers.

Ultra DMA Protocol Active)

 

 

In True IDE Mode, while DMA operations are not active, the card shall ignore the

DMACK

 

 

 

 

(-)DMACK signal, including a floating condition.

(PC Card I/O Mode when Ultra

 

 

 

 

 

 

DMA Protocol Active)

 

 

If DMA operation is not supported by a True IDE Mode only host, this signal

-DMACK

 

 

should be driven high or connected to VCC by the host.

 

 

 

 

(True IDE Mode)

 

 

A host that does not support DMA mode and implements both PC Card and

 

 

 

 

True-IDE modes of operation need not alter the PC Card mode connections

 

 

 

 

while in True-IDE mode as long as this does not prevent proper operation all

 

 

 

 

modes.

RESET

I

41

The CompactFlash Storage Card is Reset when the RESET pin is high with the

(PC Card Memory Mode)

 

 

following important exception:

 

 

 

 

The host may leave the RESET pin open or keep it continually high from the

 

 

 

 

application of power without causing a continuous Reset of the card. Under

 

 

 

 

either of these conditions, the card shall emerge from power-up having

 

 

 

 

completed an initial Reset.

 

 

 

 

The CompactFlash Storage Card is also Reset when the Soft Reset bit in the

 

 

 

 

Card Configuration Option Register is set.

RESET

 

 

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

 

 

 

 

-RESET

 

 

In the True IDE Mode, this input pin is the active low hardware reset from the

(True IDE Mode)

 

 

host.

 

 

 

 

 

 

 

 

VCC

--

13,38

+5 V, +3.3 V power.

(PC Card Memory Mode)

 

 

 

 

VCC

 

 

This signal is the same for all modes.

(PC Card I/O Mode)

 

 

 

 

VCC

 

 

This signal is the same for all modes.

(True IDE Mode)

 

 

 

 

 

 

 

 

 

 

Transcend Information Inc.

 

14

 

 

 

 

 

V1.0

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Contents Description Placement FeaturesDimensions Specification Model P/N PerformanceActual Capacity Model P/N User LBA Cylinder Head SectorBlock Diagram TS16G~64GCF400 True IDE Mode4 PC Card Memory Mode PC Card I/O ModePin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Output Drive Type Input CharacteristicsInput Leakage Current Type Parameter Symbol Conditions Output Drive CharacteristicsOutput Drive Characteristics 400X CompactFlash Card Signal DescriptionSignal Name Dir Pin Description Stschg Csel GNDPin Description Signal NameDir Intrq StopReady Dmack ResetREG Ddmardy WaitIordy DstrobeElectrical Specification CompactFlash Interface I/O atOutput Drive Characteristics for Udma mode Input Power Input Characteristics for Udma modeParameter Symbol UnitsSignal Interface Signal Card10 Host10Low state LowPull-up pin 45 BVD2 to avoid sensing their batteries as Low 150 a high state per socketTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Ieee Symbol Min ns Max ns Attribute Memory Read Timing SpecificationSymbol Speed VersionTable Configuration Register Attribute Memory Write Timing Speed Version 250 ns Symbol Min ns Max nsIeee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns MinSymbol 120 ns Min Common Memory Write Timing SpecificationCycle Time Mode 250 ns Symbol 100 ns MinMin Max Symbol Input Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns TsuHIOW TDVIWH ThHIOW TlWHDX TwHIOW TlWLIWH Output Write Timing SpecificationCycle Time Mode 255 ns 120 ns 100 ns 80 ns T6Z True IDE PIO Mode Read/Write Timing SpecificationMode TS16G~64GCF400 True IDE Multiword DMA Mode Read/Write Timing Specification True IDE Ultra DMA Mode Read/Write Timing Specification Mode Udma PC Card MEM PC Card IO Mode True IDE ModeUdma Signal Type Pin # NonTS16G~64GCF400 Name Name Comment Min Max Name Mode Mode4Udma 14.7Rising Edge Slew Rate for any signal Falling Edge Slew Rate for any signalREG Card ConfigurationMultiple Function CompactFlash Storage Cards Selected SpaceHIO Stop Dmardy Strobe Dmarq Dmack HioeDMA Inpack REGTable Attribute Memory Function Function ModeAttribute Memory Function DMA CMD REGConfiguration Option Register Base + 00h in Attribute Memory TS16G~64GCF400 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory DMA REG Table Pcmcia Mode I/O FunctionTransfer Function Hioe HiowDmarq Dmack Stop Hioe Wait DMA A10 Table PC Card I/O Mode Udma FunctionDmardy Strobe Inpack REG HiowCE2 CE1 D15-D8 D7-D0 Common Memory Transfer FunctionTable Common Memory Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS16G~64GCF400 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Command CodeDefinitions Bit Command Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Cyl High Cyl Low Sec Num Sec Cnt FeatureFlush Cache E7h Transcend Information IncErase Sectors C0h Format Track 50hIdentify Device Ech Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information BytesDefault Total Data Field Type Information CF Advanced True IDE Timing Mode Capability and Setting 164 Word 0 General ConfigurationWord 1 Default Number of Cylinders 162 0000h Key management schemes supported 163Word 49 Capabilities Bit 13 Standby Timer Word 3 Default Number of HeadsWord 6 Default Number of Sectors per Track PIO Data Transfer Cycle Timing ModeCurrent Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Multiword DMA transferWords 82-84 Features/command sets supported Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and SelectedWord 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security Status Bit 8 Security LevelMaximum Multiword DMA timing mode supported Value Current PIO timing mode selectedMaximum PIO mode timing selected Additional Requirements for CF Advanced Timing ModesMaximum Memory timing mode Supported Value Current Multiword DMA timing mode selectedMaximum Pcmcia IO timing mode Supported Value PC Card Memory or I/O Udma timing mode Selected Value Maximum PC Card I/O Udma timing mode SupportedValue Maximum PC Card Memory Udma timing mode Supported Initialize Drive Parameters 91h Idle 97h or E3hIdle Immediate 95h or E1h NOP 00hRead Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS16G~64GCF400 Seek 7Xh Set Features EFh Request Sense 03hFeature Supported TS16G~64GCF400 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS16G~64GCF400 TS16G~64GCF400 NOP Error PostingError Register Status Register BBKBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Smart Data Structure Smart Command SetSmart Command Set Smart Feature Register Values DescriptionSMI CompactFlash Card Ordering InformationTranscend Product Capacity
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