Transcend Information 400X dimensions Feature Register Address 1F1h171h Offset 1, 0Dh Write Only

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TS16G~64GCF400

400X CompactFlash Card

 

 

 

￿Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only)

This register provides information regarding features of the CompactFlash Storage Card that the host can utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high.

￿Sector Count Register (Address - 1F2h[172h]; Offset 2)

This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request.

￿Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3)

This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash Storage Card data access for the subsequent command.

￿6.1.5.5 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4)

This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address.

￿Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5)

This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address.

￿Drive/Head (LBA 27-24) Register (Address 1F6h[176h]; Offset 6)

The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing.

Bit 7: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a future revision of the specification. This bit is ignored by some controllers in some commands.

Bit 6: LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:

LBA7-LBA0: Sector Number Register D7-D0.

LBA15-LBA8: Cylinder Low Register D7-D0.

LBA23-LBA16: Cylinder High Register D7-D0.

LBA27-LBA24: Drive/Head Register bits HS3-HS0.

Bit 5: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a future revisions of the specification. This bit is ignored by some controllers in some commands.

Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card) 1 is selected. Setting this bit to 1 is obsolete in PCMCIA modes of operation. If the obsolete functionality is support by a CF Storage Card, the CompactFlash Storage Card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register.

Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode.

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Contents Dimensions Placement FeaturesDescription Specification Model P/N User LBA Cylinder Head Sector PerformanceActual Capacity Model P/NBlock Diagram TS16G~64GCF400 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O ModeTrue IDE Mode4 PC Card Memory Mode PC Card I/O Mode True IDE Mode4 Input Leakage Current Input CharacteristicsOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsType Parameter Symbol Conditions Stschg Signal DescriptionSignal Name Dir Pin Description 400X CompactFlash CardGND CselDir Signal NamePin Description Ready StopIntrq REG ResetDmack Dstrobe WaitIordy DdmardyCompactFlash Interface I/O at Electrical SpecificationUnits Input Power Input Characteristics for Udma modeParameter Symbol Output Drive Characteristics for Udma modeSignal Card10 Host10 Signal Interface150 a high state per socket LowPull-up pin 45 BVD2 to avoid sensing their batteries as Low Low stateSeries termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Speed Version Attribute Memory Read Timing SpecificationSymbol Ieee Symbol Min ns Max nsSpeed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write Timing250 ns 120 ns 100 ns 80 ns Min Common Memory Read Timing SpecificationCycle Time Mode Ieee100 ns Min Common Memory Write Timing SpecificationCycle Time Mode 250 ns Symbol Symbol 120 ns MinCycle Time Mode 250 ns 120 ns 100 ns 80 ns Input Read Timing SpecificationMin Max Symbol Cycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing SpecificationTsuHIOW TDVIWH ThHIOW TlWHDX TwHIOW TlWLIWH Mode True IDE PIO Mode Read/Write Timing SpecificationT6Z TS16G~64GCF400 True IDE Multiword DMA Mode Read/Write Timing Specification True IDE Ultra DMA Mode Read/Write Timing Specification Pin # Non PC Card MEM PC Card IO Mode True IDE ModeUdma Signal Type Mode UdmaTS16G~64GCF400 Name Name Comment 14.7 Name Mode Mode4Udma Min MaxFalling Edge Slew Rate for any signal Rising Edge Slew Rate for any signalSelected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REGInpack REG Stop Dmardy Strobe Dmarq Dmack HioeDMA HIODMA CMD REG Function ModeAttribute Memory Function Table Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS16G~64GCF400 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Hioe Hiow Table Pcmcia Mode I/O FunctionTransfer Function DMA REGInpack REG Hiow Table PC Card I/O Mode Udma FunctionDmardy Strobe Dmarq Dmack Stop Hioe Wait DMA A10Table Common Memory Function Common Memory Transfer FunctionCE2 CE1 D15-D8 D7-D0 True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address Configurations Table Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS16G~64GCF400 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command SetDefinitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit CommandFormat Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7hBytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device EchDefault Total Data Field Type Information 162 0000h Key management schemes supported 163 Word 0 General ConfigurationWord 1 Default Number of Cylinders CF Advanced True IDE Timing Mode Capability and Setting 164PIO Data Transfer Cycle Timing Mode Word 3 Default Number of HeadsWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby TimerMultiword DMA transfer Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current CapacityWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 89 Time required for Security erase unit completionAdditional Requirements for CF Advanced Timing Modes Value Current PIO timing mode selectedMaximum PIO mode timing selected Maximum Multiword DMA timing mode supportedMaximum Pcmcia IO timing mode Supported Value Current Multiword DMA timing mode selectedMaximum Memory timing mode Supported Value Maximum PC Card Memory Udma timing mode Supported Value Maximum PC Card I/O Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected NOP 00h Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91hRead DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS16G~64GCF400 Request Sense 03h Seek 7Xh Set Features EFhFeature Supported TS16G~64GCF400 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS16G~64GCF400 TS16G~64GCF400 BBK Error PostingError Register Status Register NOPBBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Description Smart Command SetSmart Command Set Smart Feature Register Values Smart Data StructureSMI Transcend Product Capacity Ordering InformationCompactFlash Card
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