H8DMT/H8DMT-IBX/H8DMT-F/H8DMT-IBXF User’s Manual
Checkpoint | Code Description | |
47h | The memory pattern has been written to extended memory. Writing patterns to | |
the base 640 KB memory next. | ||
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48h | Patterns written in base memory. Determining the amount of memory below 1 | |
MB next. | ||
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49h | The amount of memory below 1 MB has been found and verified. | |
4Ch | The memory below 1 MB has been cleared via a soft reset. Clearing the memory | |
above 1 MB next. | ||
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4Dh | The memory above 1 MB has been cleared via a soft reset. Saving the memory | |
size next. Going to checkpoint 52h next. | ||
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4Eh | The memory test started, but not as the result of a soft reset. Displaying the first | |
64 KB memory size next. | ||
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4Fh | The memory size display has started. The display is updated during the memory | |
test. Performing the sequential and random memory test next. | ||
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50h | The memory below 1 MB has been tested and initialized. Adjusting the displayed | |
memory size for relocation and shadowing next. | ||
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51h | The memory size display was adjusted for relocation and shadowing. | |
52h | The memory above 1 MB has been tested and initialized. Saving the memory | |
size information next. | ||
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53h | The memory size information and the CPU registers are saved. Entering real | |
mode next. | ||
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54h | Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, | |
parity, and the NMI next. | ||
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57h | The A20 address line, parity, and the NMI are disabled. Adjusting the memory | |
size depending on relocation and shadowing next. | ||
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58h | The memory size was adjusted for relocation and shadowing. Clearing the Hit | |
<DEL> message next. | ||
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59h | The Hit <DEL> message is cleared. The <WAIT...> message is displayed. | |
Starting the DMA and interrupt controller test next. | ||
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60h | The DMA page register test passed. Performing the DMA Controller 1 base | |
register test next. | ||
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62h | The DMA controller 1 base register test passed. Performing the DMA controller 2 | |
base register test next. | ||
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65h | The DMA controller 2 base register test passed. Programming DMA controllers 1 | |
and 2 next. | ||
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66h | Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt | |
controller next. | ||
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67h | Completed 8259 interrupt controller initialization. | |
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7Fh | Extended NMI source enabling is in progress. | |
80h | The keyboard test has started. Clearing the output buffer and checking for stuck | |
keys. Issuing the keyboard reset command next. | ||
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81h | A keyboard reset error or stuck key was found. Issuing the keyboard controller | |
interface test command next. | ||
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