4.2.1A/D Conversion Procedure
The A/D conversion is starting by a trigger source, then the A/D converter will start to convert the signal to a digital value. The
While A/D conversion, the DRDY bit in A/D status register is cleared to indicate the data is not ready. After conversion being completed, the DRDY bit will return to high(1) level. It means users can read the converted data from the A/D data registers. Please refer section 4.5 for the A/D status register format.
The A/D data should be transferred into PC's memory for further using. The
4.2.2A/D Trigger Modes
In the
If the internal trigger is selected, there are two internal sources, the software trigger and the timer pacer trigger can be used. The A/D operation mode is controlled by A/D mode bits (EITS, TSTS) of A/D control register (BASE+18). Total three trigger sources are possible in the
Software trigger
The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register (BASE+20). This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled under software. However, it is difficult to control the fixed A/D conversion rate except another timer interrupt service routine is used to generate a fixed rate trigger.
Timer Pacer Trigger
An