HP 9112 1 A/D Conversion Procedure, 2 A/D Trigger Modes, Software trigger, Timer Pacer Trigger

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4.2.1A/D Conversion Procedure

The A/D conversion is starting by a trigger source, then the A/D converter will start to convert the signal to a digital value. The PCI-9112 provides three trigger modes, see section 5.1.2.

While A/D conversion, the DRDY bit in A/D status register is cleared to indicate the data is not ready. After conversion being completed, the DRDY bit will return to high(1) level. It means users can read the converted data from the A/D data registers. Please refer section 4.5 for the A/D status register format.

The A/D data should be transferred into PC's memory for further using. The PCI-9112 provides three data transfer modes that allow users to optimize the DAS system. Refer to section 5.1.3 for data transfer modes.

4.2.2A/D Trigger Modes

In the PCI-9112, A/D conversion can be triggered by the Internal or External trigger source. The EITS bit of A/D control register is used to select the internal or external trigger, please refer to section 4.5 for details. Whenever the external source is set, the internal sources are disable.

If the internal trigger is selected, there are two internal sources, the software trigger and the timer pacer trigger can be used. The A/D operation mode is controlled by A/D mode bits (EITS, TSTS) of A/D control register (BASE+18). Total three trigger sources are possible in the PCI-9112. The different trigger conditions are specified as follows:

Software trigger

The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register (BASE+20). This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled under software. However, it is difficult to control the fixed A/D conversion rate except another timer interrupt service routine is used to generate a fixed rate trigger.

Timer Pacer Trigger

An on-board timer / counter chip 8254 is used to provide a trigger source for A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period. Please refer to section 5.4 for 8254 architecture. This mode is ideal for high speed A/D conversion. It can be combined with the DMA bus mastering or the interrupt data transfer. It's recommend to use this mode if your applications need a fixed and precise A/D sampling rate.

Operation Theorem ∙ 31

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Contents Page Trademarks ALL Rights ReservedAdlink Technology Inc Detailed Company InformationQuestions Page Contents 9112DblBufferTransfer 9112GetOverrunStatus ConversionConversion Digital Input and Output 9112DO 9112DA 9112ADSetChannel 9112ADSetRangePCI Scan Utility Appendix A. Demo. Programs Product Warranty/ServiceWhat do you need VR Assignment Adjustment Software UtilitiesHow to Use This Guide Features T r o d u c t i o nIntroduction ∙ Analog Output D/A SpecificationsApplications Analog Input A/DGeneral Specifications Digital I/O DIOProgrammable Counter Software Supporting Programming LibraryPCIS-LVIEW LabVIEW Driver PCIS-DDE DDE Server and InTouchTM PCIS-VEE HP-VEE DriverDAQBenchTM ActiveX Controls DASYLabTM PROInstallation ∙ InstallationWhat You Have Device Installation for Windows Systems Installation ∙Unpacking PCI -Bus Controller PCB LayoutPCI-9112 Layout ConverterPCB Layout of the PCI-9112 CPCI-9112 LayoutJumper Settings Analog Input Channel Configuration10 ∙ Installation D/A Reference Voltage Setting Clock Source Setting12 ∙ Installation Internal Reference Voltage SettingConnectors Pin Assignments CN 3 Analog Input / Output & Counter/TimerPin Assignments of PCI-9112 CN 1 Digital Signal Input DI 0 CN 2 Digital Signal Output do 014 ∙ Installation Pin Assignments of cPCI-9112 16 ∙ Installation Hardware Installation OutlineConnect with ACLD-9182 Daughter Board ConnectionConnect with ACLD-8125 Connect with ACLD-913718 ∙ Installation Connect with ACLD-9185Connect with ACLD-9138 and ACLD-9188 G i s t e r s F o r m a t I/O Registers MapRegisters Format ∙ 20 ∙ Registers Format A/D Data RegistersD/A Output Register A/D control Register Mode22 ∙ Registers Format MUX Register Bit8 ~ Bit5 Auto-Scan Bit24 ∙ Registers Format Software Trigger Register A/D Status Register26 ∙ Registers Format Digital I/O registerInternal Timer/Counter Register High Level ProgrammingLow Level Programming 28 ∙ Operation Theorem Analog Input Signal ConnectionE r a t i o n T h e o r e m A/D ConversionSingle-ended Mode Differential input modeOperation Theorem ∙ 30 ∙ Operation Theorem 4 Floating source and differential inputSoftware trigger 1 A/D Conversion ProcedureTimer Pacer Trigger 2 A/D Trigger ModesInterrupt Transfer Intx 3 A/D Data Transfer ModesExternal Trigger Software Data Transfer DrdyDMA Transfer Dmax D/A Conversion34 ∙ Operation Theorem Digital Input and OutputCounter Timer/Counter Operation36 ∙ Operation Theorem General Purpose Timer/ CounterPacer Trigger Source AddressControl Byte 38 ∙ Operation Theorem Mode DefinitionsLibraries Installation + + L i b r a r y++ Library ∙ 40 ∙ C/C++ Library Programming GuideNaming Convention Data TypesReturn Code 9112InitialSyntax Argument42 ∙ C/C++ Library 9112DI9112DI Channel Description9112DO 44 ∙ C/C++ Library 9112DA9112ADSetChannel 46 ∙ C/C++ Library 9112ADSetRangeCardnumber the card number of PCI-9112 10 9112ADSetMode48 ∙ C/C++ Library 11 9112ADSetAutoscan12 9112ADSoftTrig 50 ∙ C/C++ Library 13 9112ADAquire14 9112ADDMAStart 52 ∙ C/C++ Library 15 9112ADDMAStatus 54 ∙ C/C++ Library 16 9112ADDMAStop17 9112ContDmaStart 56 ∙ C/C++ Library 18 9112CheckHalfReady20 9112GetOverrunStatus 19 9112DblBufferTransfer58 ∙ C/C++ Library 21 9112ContDmaStop22 9112ADINTStart 60 ∙ C/C++ Library 23 9112ADINTStatus24 9112ADINTStop 25 9112ADTimer62 ∙ C/C++ Library 2MHz / c1 * c227 9112TIMERRead 26 9112TIMERStart64 ∙ C/C++ Library 28 9112TIMERStop29 9112AllocDMAMem Argument cardnumber countervalue32 9112GetSample 30 9112FreeDMAMem66 ∙ C/C++ Library Calibration What do you needCalibration ∙ Unipolar Calibration A/D AdjustmentVR Assignment Bipolar CalibrationD/A Adjustment Reference Voltage Calibration2 D/A Channel Calibration Software Utilities Software Utility70 ∙ Software Utility Software Utility ∙ System ConfigurationRunning the Utility CalibrationFunctional Testing PCI Scan Utility72 ∙ Software Utility Appendix a Demo Programs ∙ P e n d i x a . D e m o O g r a m sDOS Software Windows 95 DLL74 ∙ Appendix a Demo Programs Product Warranty/Service ∙ Product Warranty/Service
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