Fujitsu MB91401 Rxclk, Rxer, Rxdv, Rxcrs, RXD3, RXD2, RXD1, RXD0, Col, Txclk, Txen OUT, TXD3

	Prelminary					MB91401
2004.11.12
	ETHERNET MAC CONTROLLER (17 pin)
	Pin name	Pin no.	Polarity	I/O	Circuit	Function/application
						Clock input for reception pin
	RXCLK	48		IN	D	MII sync signal during reception. The frequency is 2.5 MHz
						at 10 Mbps and 25 MHz at 100 Mbps.
			Posi-			Receive error input pin
	RXER	113		IN	D	It is recognized that there is an error in the reception packet
			tive
						when “1” is input from the PHY device at receiving.
	RXDV	172	Posi-	IN	D	Receive data valid input pin
			tive			It is recognized that receive data is effective.
			Posi-			Career sense input pin
	RXCRS	115		IN	D	The state that the reception or the transmission is done is
			tive
						recognized.
	RXD3	114
	RXD2	47		IN	D	Receive data input pins
	RXD1	112				4-bit data input from PHY device.
	RXD0	45
						Collision detection input pin
	COL	173	Posi-	IN	D	When TXEN signal is active and “1”, the collision is
			tive			recognized. The collision is not recognized without these
						conditions.
						Clock input for transfer pin
	TXCLK	46		IN	D	It becomes synchronous of MII when transmitting. The
						frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.
			Posi-			Transfer enable output pin
	TXEN	43		OUT	F	It is shown that effective data is on the TXD bus. It is output
			tive
						synchronizing with TXCLK.
	TXD3	171				Transfer data output pins
	TXD2	170	
				OUT	F	4-bit data bus sent to the PHY device. It is output
	TXD1	111
						synchronizing with TXCLK.
	TXD0	44
						SMI clock output pin
	MDCLK	222		OUT	F	SMI IF clock pin
						Connect to SMI clock input pin of PHY device.
	MDIO	224		I/O	B	SMI data input/output pin
						Connect to SMI data of PHY device.

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