Fujitsu MB91401 manual Andh, Andb, Orh, Orb, Eorh, Eorb, Xchb

Page 26

MB91401

Prelminary

2004.11.12

 

 

CPU

•The instruction fetch is not done from D-bus, and does not set the code area on D-bus RAM.

•Set neither stack area nor the vector table on the instruction RAM.

•The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu:

(1)The D0 and D1 flags are updated in advance.

(2)An EIT handling routine (user interrupt, NMI, or emulator) is executed.

(3)Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1) .

•The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.

(1)The PS register is updated in advance.

(2)Executing of EIT processing routine (user interrupt • NMI)

(3)Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1) .

•Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the micro- controller is designed to carry out reprocessing correctly upon returning from such an EIT event in either case, it performs operations before and after the EIT as specified.

1.When (a) user interrupt and NMI are accepted or (b) step is executed or (c) break is done by the data event or the menu of the emulator in the instruction immediately before the instruction of DIV0U/DIV0S, the following operation might be done.

(1)The D0 and D1 flags are updated in advance.

(2)An EIT handling routine (user interrupt, NMI, or emulator) is executed.

(1)Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (3) .

2.When ORCCR, STILM, MOV Ri, and PS each instruction is executed to permit interrupt with the user interrupt and the NMI factor generated, the following operation is done.

(1)The PS register is updated in advance.

(2)The EIT processing routine (user interrupt, NMI or emulator) is executed.

(3)Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1).

•Do not access the data to the cache memory at the control register of the instruction cash and RAM mode immediately before the instruction of RETI.

•If one of the instructions listed below is executed, the SSP or USP* value is not used as the R15 value and, as a result, an incorrect value is written to memory.

•Only ten following kinds of instructions that specify R15 as Ri correspond.

AND

R15, @Rj

ANDH

R15, @Rj

ANDB

R15, @Rj

OR

R15, @Rj

ORH

R15, @Rj

ORB

R15, @Rj

EOR

R15, @Rj

EORH

R15, @Rj

EORB

R15, @Rj

XCHB

@Rj, R15

 

 

 

 

*: As for R15, there are no realities. When R15 is accessed from the program, SSP or USP is accessed by the state of "S" flag of the PS register. Please specify general registers other than R15 when ten above-mentioned instructions are described by the assembler.

26

Page 25 Page 27
Image 26
Page 25 Page 27
Contents Package FeaturesDescription Memory Interface Packet filtering functionGeneral Purpose IO Gpio USB Function ControllerCard Interface CompactFlash I2C InterfacePIN Assignment Index E F G H J K L M N P R T U V WPIN Number Table PIN Description GNDPin name Pin no Function/applicationICS1 OUT BreakiICS2 ICS0SOUT1 SIN1SIN0 SOUT0MB91401 Rxdv RxclkRxer RxcrsEXD15 ExcsxEXA EXD14Usbins UDPUDM UCLK48CFD10 CFD9 CFD15 CFD14 CFD13 CFD12CFD11 CFD8MB91401 Pllvdd SDASCL PllvssUSB I/O Circuit TypeType Circuit Remarks Circuit Remarks Preventing Latch-up Separation of power supply patternHandling Devices Treatment of output pins Treatment of the unused pinsTreatment of Open pins About power supply pinsConnected Specification of MB91401 and ICE Attached cable Part number RemarksRST Signal line name Wiring regulationsEvaluation MCU terminal name Pin treatment UV CCCircuit constants Description Pin name FunctionOsceb Bit data bus Holding request withdrawal demand function OFFAbout watch dog timer Treatment of Unused Input PinsAbout Mode pins MDI2 to MDI0 Operation at start-upORH AndhAndb ORBDMA Operand break Trace modeStep execution of Reti instruction Interrupt handler to NMI request toolBlock Diagram Authentication macroMemory Space General Purpose Registers Mode Register Modr Mode SettingsMode Pins RegisterFunction Remarks Bit1, bit0 WTH1, WTH0 Bus width setting bitsOperation mode MAP Address Register BlockSIDR0 R/W DRCL0 W UTIMC0 R/W TIMER0DRCL1 W UTIMC1 R/W TIMER1 UART0BSD1 Xxxxxxxx Ichrc R/WBSD0 Xxxxxxxx BsdcAddress Register Block DMASA1 Xxxxxxxx DMASA0 XxxxxxxxDMADA0 Xxxxxxxx DMADA1 XxxxxxxxDARR/W BC2RR/W Xxxxxxxx Bsrr BCRR/W CCRR/W ADRR/W1XXXXXXX 010FFFFF HSmicmdst Smistatusr SIM if Xxxxxxxx SmiintenableSMICMDR/W 00XXXXXX SIM ifExifrxrr Exifrxdr RExiftxdr W ExiftxrwFIFO3W XXXXXXXX-XXXXXXXX XXXXXXXX-XXXXXXXXFIFO1R FIFO2W XXXXXXXX-XXXXXXXX CONT1R/W XXXXX0XX-XXX00000XXXXXXXX-X0000000 XXXXXXXX-XXX00000 Interrupt Vector Interrupt Address of TBR Interrupt source OffsetDefault Interrupt Address of TBR Interrupt source Offset NMI Non Maskable InterruptMin Electrical CharacteristicsParameter Symbol Rating Unit ΣiolParameter Symbol Value Unit TypPin Conditions Value Unit Min Typ CfresetParameter TCK/TRST/TMS TDI/TDOPin Conditions Value Unit Input Levels High driven Vcrs standard range Mclko VDDE/2Usbc Unit Remarks Min Reset ParameterPin Conditions Mclko ↑ RDX Mclko ↑RDY Mclko ↑ SIN1, SIN0 SCK1, SCK0SOUT1, SOUT0 Sclk ↑Internal shift clock mode Rxer Rxclk ↑ Txen Txclk ↑Rxdv Rxclk ↑ Reception Mdio Mdclk ↑ OUT →Parameter Symbol Pin Value Unit Remarks Min External ifWrite access USB interface Parameter Symbol Pin UDP, UDMFull-speed Buffer SCL Pclk 10 I2C interfacePclk SDA PclkCFOEX, Cfiordx Card ifCFCE2X, CFCE1X CFWEX, Cfiowrx Parameter SymbolValue Unit Remarks Min Max CDWEX, CfiowrxOrdering Information Part number Package RemarksPackage Dimension Memo Europe JapanNorth and South America Asia Pacific

MB91401 specifications

The Fujitsu MB91401 microcontroller is a versatile device designed for automotive applications, embedded systems, and industrial control. It belongs to the MB91400 series, known for its robustness and efficiency. This series integrates advanced features and technologies that cater to a wide variety of real-time applications.

One of the standout features of the MB91401 is its 32-bit RISC architecture, which operates at clock speeds up to 40 MHz. This high-performance core enables rapid processing and data handling, making it suitable for demanding applications. The microcontroller is equipped with a generous amount of Flash memory, allowing developers to store essential firmware and applications directly on the chip, enhancing reliability and reducing design complexity.

Another key characteristic is its extensive memory configuration, which includes SRAM for data storage and EEPROM for non-volatile data retention. This combination provides flexibility for developers, enabling them to tailor the memory allocation based on specific application requirements.

The MB91401 is designed with a focus on peripheral integration. It features multiple I/O ports, timer units, and A/D converters, making it an ideal choice for applications that require precise timing and analog signal processing. The analog-to-digital converters offer high resolution and fast conversion speeds, which are critical in automotive and industrial control systems where accuracy is paramount.

Safety is a critical consideration in automotive applications, and the MB91401 addresses this with built-in diagnostic features and error detection capabilities. These features help ensure that the application remains functional and safe under various operating conditions.

In terms of connectivity, the microcontroller supports various communication protocols, including CAN, UART, and SPI, facilitating seamless integration with other systems and devices. This is particularly important in automotive applications where communication between different electronic control units (ECUs) is essential for overall system functionality.

The Fujitsu MB91401 is also designed for low power consumption, making it suitable for battery-operated devices and energy-sensitive applications. Its various power-saving modes allow developers to optimize the system's performance while extending operational life.

In summary, the Fujitsu MB91401 is a powerful and flexible microcontroller that combines high-performance processing with extensive peripheral support and safety features. Its robust architecture and energy-efficient design make it an excellent choice for a wide range of automotive and industrial applications, promoting both reliability and innovation in embedded system development.
Top Page Image Contents