Fujitsu MB91401 manual Bit data bus, Holding request withdrawal demand function OFF

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MB91401

 

 

 

Prelminary

 

 

 

2004.11.12

 

 

 

 

 

 

 

 

 

• Reference Value

 

 

 

 

 

 

Oscillation frequency

C1, C2

C3

L

Rr

 

 

 

 

 

 

 

 

 

to 30 MHz

5 pF to 33 pF

None

None

None

 

 

 

 

 

 

 

 

 

20 MHz to 50 MHz

5 pF to 15 pF

10 nF approx.

1 ∝H approx.

None

 

 

 

 

 

 

 

 

It is necessary to add C3/L depending on a basic wave and the over tone characteristic of the oscillator of the 20 MHz to 30 MHz belt.

Note : These reference values are standards. The constant changes according to the characteristic of the quartz vibrator used. Therefore, we will recommend the initial evaluation that uses the evaluation sample to the decision of the circuit constant. Please contact FUJITSU representatives about the evaluation sample.

•Notes when encryption/authentication accelarator is used

When using the encryption/authentication installed in this LSI, it is necessary to the following notes.

32-bit data bus

The encryption/authentication accelerator fetches data from the area storing data to be subject to encryption/ authentication and encrypts or authenticates the data without CPU intervention. In the encryption processing, write is done in the area where it wants to store the data after the encryption is processed.

encryption/

authentication

accelerator

MB91401

32bit

Data Bus

RAM

At the storage destination of

encryption/authentication

processing data

Holding request withdrawal demand function OFF

When accessing to the storage destination of encryption/authentication processing data, the encryption/authen- tication accelerator should hold an internal bus of this LSI.

Therefore, when the encryption/authentication accelerator are used, it should be set that the holding request withdrawal doesn’t demand.

Please set the HRCL register that sets the interrupt level that becomes the standard of the holding request withdrawal demand generation to "10000" in the FR core.

For NMIs, the hold request cancel request occurs regardless of the HRCL register setting. When the encryption/ authentication accelerator is used, therefore, NMI input may cause encryption/authentication to fail to result correctly. In that case, the correspondence said that it will execute the encryption/authentication processing under execution again is necessary.

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Contents Features DescriptionPackage Packet filtering function General Purpose IO GpioMemory Interface USB Function ControllerCard Interface CompactFlash I2C InterfacePIN Assignment Index E F G H J K L M N P R T U V WPIN Number Table PIN Description GNDPin name Pin no Function/applicationBreaki ICS2ICS1 OUT ICS0SIN1 SIN0SOUT1 SOUT0MB91401 Rxclk RxerRxdv RxcrsExcsx EXAEXD15 EXD14UDP UDMUsbins UCLK48CFD15 CFD14 CFD13 CFD12 CFD11CFD10 CFD9 CFD8MB91401 SDA SCLPllvdd PllvssCircuit Type Type Circuit RemarksUSB I/O Circuit Remarks Separation of power supply pattern Handling DevicesPreventing Latch-up Treatment of the unused pins Treatment of Open pinsTreatment of output pins About power supply pinsConnected Specification of MB91401 and ICE Attached cable Part number RemarksSignal line name Wiring regulations Evaluation MCU terminal name Pin treatmentRST UV CCPin name Function OscebCircuit constants Description Bit data bus Holding request withdrawal demand function OFFTreatment of Unused Input Pins About Mode pins MDI2 to MDI0About watch dog timer Operation at start-upAndh AndbORH ORBDMA Trace mode Step execution of Reti instructionOperand break Interrupt handler to NMI request toolBlock Diagram Authentication macroMemory Space General Purpose Registers Mode Settings Mode PinsMode Register Modr RegisterBit1, bit0 WTH1, WTH0 Bus width setting bits Operation modeFunction Remarks MAP Address Register BlockDRCL0 W UTIMC0 R/W TIMER0 DRCL1 W UTIMC1 R/W TIMER1SIDR0 R/W UART0Ichrc R/W BSD0 XxxxxxxxBSD1 Xxxxxxxx BsdcAddress Register Block DMASA0 Xxxxxxxx DMADA0 XxxxxxxxDMASA1 Xxxxxxxx DMADA1 XxxxxxxxBsrr BCRR/W CCRR/W ADRR/W 1XXXXXXXDARR/W BC2RR/W Xxxxxxxx 010FFFFF HSmistatusr SIM if Xxxxxxxx Smiintenable SMICMDR/WSmicmdst 00XXXXXX SIM ifExifrxdr R Exiftxdr WExifrxrr ExiftxrwXXXXXXXX-XXXXXXXX FIFO1R FIFO2W XXXXXXXX-XXXXXXXXFIFO3W XXXXXXXX-XXXXXXXX CONT1R/W XXXXX0XX-XXX00000XXXXXXXX-X0000000 XXXXXXXX-XXX00000 Interrupt Vector Interrupt Address of TBR Interrupt source OffsetDefault Interrupt Address of TBR Interrupt source Offset NMI Non Maskable InterruptElectrical Characteristics Parameter Symbol Rating UnitMin ΣiolParameter Symbol Value Unit TypCfreset ParameterPin Conditions Value Unit Min Typ TCK/TRST/TMS TDI/TDOPin Conditions Value Unit Input Levels High driven Vcrs standard range VDDE/2 UsbcMclko Reset Parameter Pin ConditionsUnit Remarks Min Mclko ↑ RDX Mclko ↑RDY Mclko ↑ SCK1, SCK0 SOUT1, SOUT0SIN1, SIN0 Sclk ↑Internal shift clock mode Txen Txclk ↑ Rxdv Rxclk ↑Rxer Rxclk ↑ Reception Mdio Mdclk ↑ OUT →Parameter Symbol Pin Value Unit Remarks Min External ifWrite access USB interface Parameter Symbol Pin UDP, UDMFull-speed Buffer 10 I2C interface PclkSCL Pclk SDA PclkCard if CFCE2X, CFCE1XCFOEX, Cfiordx Parameter Symbol Value Unit Remarks Min MaxCFWEX, Cfiowrx CDWEX, CfiowrxOrdering Information Part number Package RemarksPackage Dimension Memo Japan North and South AmericaEurope Asia Pacific

MB91401 specifications

The Fujitsu MB91401 microcontroller is a versatile device designed for automotive applications, embedded systems, and industrial control. It belongs to the MB91400 series, known for its robustness and efficiency. This series integrates advanced features and technologies that cater to a wide variety of real-time applications.

One of the standout features of the MB91401 is its 32-bit RISC architecture, which operates at clock speeds up to 40 MHz. This high-performance core enables rapid processing and data handling, making it suitable for demanding applications. The microcontroller is equipped with a generous amount of Flash memory, allowing developers to store essential firmware and applications directly on the chip, enhancing reliability and reducing design complexity.

Another key characteristic is its extensive memory configuration, which includes SRAM for data storage and EEPROM for non-volatile data retention. This combination provides flexibility for developers, enabling them to tailor the memory allocation based on specific application requirements.

The MB91401 is designed with a focus on peripheral integration. It features multiple I/O ports, timer units, and A/D converters, making it an ideal choice for applications that require precise timing and analog signal processing. The analog-to-digital converters offer high resolution and fast conversion speeds, which are critical in automotive and industrial control systems where accuracy is paramount.

Safety is a critical consideration in automotive applications, and the MB91401 addresses this with built-in diagnostic features and error detection capabilities. These features help ensure that the application remains functional and safe under various operating conditions.

In terms of connectivity, the microcontroller supports various communication protocols, including CAN, UART, and SPI, facilitating seamless integration with other systems and devices. This is particularly important in automotive applications where communication between different electronic control units (ECUs) is essential for overall system functionality.

The Fujitsu MB91401 is also designed for low power consumption, making it suitable for battery-operated devices and energy-sensitive applications. Its various power-saving modes allow developers to optimize the system's performance while extending operational life.

In summary, the Fujitsu MB91401 is a powerful and flexible microcontroller that combines high-performance processing with extensive peripheral support and safety features. Its robust architecture and energy-efficient design make it an excellent choice for a wide range of automotive and industrial applications, promoting both reliability and innovation in embedded system development.
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