Fujitsu MB91401 Step execution of Reti instruction, Operand break, Location to added, Trace mode

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MB91401

Prelminary

2004.11.12

 

 

■NOTES OF DEBUG

Step execution of RETI instruction

In an environment where interrupts frequently occur during single-step execution, only the relevant interrupt processing routines are executed repeatedly during single-step execution of the RETI instruction. This will prevent the main routine and low-interrupt-level programs from being executed.

Do not execute step of RETI instruction for escape.

When the relevant interrupt routine no longer requires being debugged, disable the relevant interrupt and perform debugging.

Operand break

Do not set the access which is used for area, including the address of system stack pointer, to the target of data event break.

Interrupt handler to NMI request (tool)

To prevent the malfunction because of the noise problem of DSU pin when ICE is unconnected, the following programs are added to the interrupt handler by the cause flag, which is only set by the break request from ICE. ICE can be used even if this program is added.

Location to added

The following interrupt handler

Interrupt resource

: NMI request (tool)

Interrupt number

: 13 (decimal), 0D (hexadecimal)

Offset

: 3C8H

TBR is default address.

: 000FFFC8H

Additional program

STM

(R0, R1)

 

LDI

#B00H, R0

; B00H is address of the break resource register.

LDI #0, R1

 

STB

R1, @R0

; Clear the break resource register.

LDM

(R0, R1)

 

RETI

Trace mode

If the trace mode is set to "Full trace mode" during debug (in full trace mode, built-in FIFO is used as output buffer, the trace memory of the main body of ICE is used, and the trace data lost is not occurred), the electric current is increased and D-busDMA access may be lost.

Also, the trace data lost may be occurred.

To take the measures, do not set full trace mode.

Simultaneous generation of a software break and a user interrupt/NMI

When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as follows.

•The debugger stops pointing to a location other than the programmed breakpoints.

•The halted program is not re-executed correctly.

When these problems are occurred, not only the software break, the hardware break should also be used. Do not set the break to the corresponding location when using monitor debugger.

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Contents Description FeaturesPackage Packet filtering function General Purpose IO GpioMemory Interface USB Function ControllerCard Interface CompactFlash I2C InterfacePIN Assignment Index E F G H J K L M N P R T U V WPIN Number Table PIN Description GNDPin name Pin no Function/applicationBreaki ICS2ICS1 OUT ICS0SIN1 SIN0SOUT1 SOUT0MB91401 Rxclk RxerRxdv RxcrsExcsx EXAEXD15 EXD14UDP UDMUsbins UCLK48CFD15 CFD14 CFD13 CFD12 CFD11CFD10 CFD9 CFD8MB91401 SDA SCLPllvdd PllvssType Circuit Remarks Circuit TypeUSB I/O Circuit Remarks Handling Devices Separation of power supply patternPreventing Latch-up Treatment of the unused pins Treatment of Open pinsTreatment of output pins About power supply pinsConnected Specification of MB91401 and ICE Attached cable Part number RemarksSignal line name Wiring regulations Evaluation MCU terminal name Pin treatmentRST UV CCOsceb Pin name FunctionCircuit constants Description Bit data bus Holding request withdrawal demand function OFFTreatment of Unused Input Pins About Mode pins MDI2 to MDI0About watch dog timer Operation at start-upAndh AndbORH ORBDMA Trace mode Step execution of Reti instructionOperand break Interrupt handler to NMI request toolBlock Diagram Authentication macroMemory Space General Purpose Registers Mode Settings Mode PinsMode Register Modr RegisterOperation mode Bit1, bit0 WTH1, WTH0 Bus width setting bitsFunction Remarks MAP Address Register BlockDRCL0 W UTIMC0 R/W TIMER0 DRCL1 W UTIMC1 R/W TIMER1SIDR0 R/W UART0Ichrc R/W BSD0 XxxxxxxxBSD1 Xxxxxxxx BsdcAddress Register Block DMASA0 Xxxxxxxx DMADA0 XxxxxxxxDMASA1 Xxxxxxxx DMADA1 XxxxxxxxBsrr BCRR/W CCRR/W ADRR/W 1XXXXXXXDARR/W BC2RR/W Xxxxxxxx 010FFFFF HSmistatusr SIM if Xxxxxxxx Smiintenable SMICMDR/WSmicmdst 00XXXXXX SIM ifExifrxdr R Exiftxdr WExifrxrr ExiftxrwXXXXXXXX-XXXXXXXX FIFO1R FIFO2W XXXXXXXX-XXXXXXXXFIFO3W XXXXXXXX-XXXXXXXX CONT1R/W XXXXX0XX-XXX00000XXXXXXXX-X0000000 XXXXXXXX-XXX00000 Interrupt Vector Interrupt Address of TBR Interrupt source OffsetDefault Interrupt Address of TBR Interrupt source Offset NMI Non Maskable InterruptElectrical Characteristics Parameter Symbol Rating UnitMin ΣiolParameter Symbol Value Unit TypCfreset ParameterPin Conditions Value Unit Min Typ TCK/TRST/TMS TDI/TDOPin Conditions Value Unit Input Levels High driven Vcrs standard range Usbc VDDE/2Mclko Pin Conditions Reset ParameterUnit Remarks Min Mclko ↑ RDX Mclko ↑RDY Mclko ↑ SCK1, SCK0 SOUT1, SOUT0SIN1, SIN0 Sclk ↑Internal shift clock mode Rxdv Rxclk ↑ Txen Txclk ↑Rxer Rxclk ↑ Reception Mdio Mdclk ↑ OUT →Parameter Symbol Pin Value Unit Remarks Min External ifWrite access USB interface Parameter Symbol Pin UDP, UDMFull-speed Buffer 10 I2C interface PclkSCL Pclk SDA PclkCFCE2X, CFCE1X Card ifCFOEX, Cfiordx Parameter Symbol Value Unit Remarks Min MaxCFWEX, Cfiowrx CDWEX, CfiowrxOrdering Information Part number Package RemarksPackage Dimension Memo Japan North and South AmericaEurope Asia Pacific

MB91401 specifications

The Fujitsu MB91401 microcontroller is a versatile device designed for automotive applications, embedded systems, and industrial control. It belongs to the MB91400 series, known for its robustness and efficiency. This series integrates advanced features and technologies that cater to a wide variety of real-time applications.

One of the standout features of the MB91401 is its 32-bit RISC architecture, which operates at clock speeds up to 40 MHz. This high-performance core enables rapid processing and data handling, making it suitable for demanding applications. The microcontroller is equipped with a generous amount of Flash memory, allowing developers to store essential firmware and applications directly on the chip, enhancing reliability and reducing design complexity.

Another key characteristic is its extensive memory configuration, which includes SRAM for data storage and EEPROM for non-volatile data retention. This combination provides flexibility for developers, enabling them to tailor the memory allocation based on specific application requirements.

The MB91401 is designed with a focus on peripheral integration. It features multiple I/O ports, timer units, and A/D converters, making it an ideal choice for applications that require precise timing and analog signal processing. The analog-to-digital converters offer high resolution and fast conversion speeds, which are critical in automotive and industrial control systems where accuracy is paramount.

Safety is a critical consideration in automotive applications, and the MB91401 addresses this with built-in diagnostic features and error detection capabilities. These features help ensure that the application remains functional and safe under various operating conditions.

In terms of connectivity, the microcontroller supports various communication protocols, including CAN, UART, and SPI, facilitating seamless integration with other systems and devices. This is particularly important in automotive applications where communication between different electronic control units (ECUs) is essential for overall system functionality.

The Fujitsu MB91401 is also designed for low power consumption, making it suitable for battery-operated devices and energy-sensitive applications. Its various power-saving modes allow developers to optimize the system's performance while extending operational life.

In summary, the Fujitsu MB91401 is a powerful and flexible microcontroller that combines high-performance processing with extensive peripheral support and safety features. Its robust architecture and energy-efficient design make it an excellent choice for a wide range of automotive and industrial applications, promoting both reliability and innovation in embedded system development.
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