Fujitsu MB91401 Interrupt Address of TBR Interrupt source Offset, NMI Non Maskable Interrupt

Page 46

MB91401

 

 

 

 

Prelminary

 

 

 

 

2004.11.12

 

 

 

 

 

 

 

 

 

 

 

(Continued)

 

 

 

 

 

 

 

 

 

Interrupt number

Interrupt

 

Address of TBR

 

 

 

Interrupt source

 

 

Offset

RN

 

 

Decimal

Hexa-

level

default

 

 

 

 

 

 

 

 

 

decimal

 

 

 

 

 

 

System reserved

68

44

2ECH

000FFEECH

 

 

 

 

 

 

 

 

 

 

 

System reserved

69

45

2E8H

000FFEE8H

 

 

 

 

 

 

 

 

 

 

 

System reserved

70

46

2E4H

000FFEE4H

 

 

 

 

 

 

 

 

 

 

 

System reserved

71

47

2E0H

000FFEE0H

 

 

 

 

 

 

 

 

 

 

 

System reserved

72

48

2DCH

000FFEDCH

 

 

 

 

 

 

 

 

 

 

 

System reserved

73

49

2D8H

000FFED8H

 

 

 

 

 

 

 

 

 

 

 

System reserved

74

4A

2D4H

000FFED4H

 

 

 

 

 

 

 

 

 

 

 

System reserved

75

4B

2D0H

000FFED0H

 

 

 

 

 

 

 

 

 

 

 

System reserved

76

4C

2CCH

000FFECCH

 

 

 

 

 

 

 

 

 

 

 

System reserved

77

4D

2C8H

000FFEC8H

 

 

 

 

 

 

 

 

 

 

 

System reserved

78

4E

2C4H

000FFEC4H

 

 

 

 

 

 

 

 

 

 

 

System reserved

79

4F

2C0H

000FFEC0H

 

 

 

 

 

 

 

 

 

 

 

 

80

50

2BCH

000FFEBCH

 

 

Used by INT instruction

to

to

to

to

 

 

 

255

FF

 

000H

000FFC00H

 

 

 

 

 

 

 

 

 

 

 

(2) NMI (Non Maskable Interrupt)

NMIs have the highest priority among the interrupt sources handled by this module.

An NMI is always selected whenever other types of interrupt sources occur at the same time.

•If an NMI occurs, the interrupt controller passes the information to the CPU : Interrupt level : 15 (01111B)

Interrupt number : 15 (0001111B)

•NMI detection

NMIs are set and detected by the external interrupt/NMI controller. This module only generates an interrupt level, interrupt number, and MHALTI upon NMI request.

•Suppressing DMA transfer upon NMI request

When an NMI request occurs, the MHALTI bit in the HRCL register is set to "1", suppressing DMA transfer. To permit DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.

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Contents Description FeaturesPackage Memory Interface Packet filtering functionGeneral Purpose IO Gpio USB Function ControllerCard Interface CompactFlash I2C InterfacePIN Assignment Index E F G H J K L M N P R T U V WPIN Number Table PIN Description GNDPin name Pin no Function/applicationICS1 OUT BreakiICS2 ICS0SOUT1 SIN1SIN0 SOUT0MB91401 Rxdv RxclkRxer RxcrsEXD15 ExcsxEXA EXD14Usbins UDPUDM UCLK48CFD10 CFD9 CFD15 CFD14 CFD13 CFD12CFD11 CFD8MB91401 Pllvdd SDASCL PllvssType Circuit Remarks Circuit TypeUSB I/O Circuit Remarks Handling Devices Separation of power supply patternPreventing Latch-up Treatment of output pins Treatment of the unused pinsTreatment of Open pins About power supply pinsConnected Specification of MB91401 and ICE Attached cable Part number RemarksRST Signal line name Wiring regulationsEvaluation MCU terminal name Pin treatment UV CCOsceb Pin name FunctionCircuit constants Description Bit data bus Holding request withdrawal demand function OFFAbout watch dog timer Treatment of Unused Input PinsAbout Mode pins MDI2 to MDI0 Operation at start-upORH AndhAndb ORBDMA Operand break Trace modeStep execution of Reti instruction Interrupt handler to NMI request toolBlock Diagram Authentication macroMemory Space General Purpose Registers Mode Register Modr Mode SettingsMode Pins RegisterOperation mode Bit1, bit0 WTH1, WTH0 Bus width setting bitsFunction Remarks MAP Address Register BlockSIDR0 R/W DRCL0 W UTIMC0 R/W TIMER0DRCL1 W UTIMC1 R/W TIMER1 UART0BSD1 Xxxxxxxx Ichrc R/WBSD0 Xxxxxxxx BsdcAddress Register Block DMASA1 Xxxxxxxx DMASA0 XxxxxxxxDMADA0 Xxxxxxxx DMADA1 XxxxxxxxDARR/W BC2RR/W Xxxxxxxx Bsrr BCRR/W CCRR/W ADRR/W1XXXXXXX 010FFFFF HSmicmdst Smistatusr SIM if Xxxxxxxx SmiintenableSMICMDR/W 00XXXXXX SIM ifExifrxrr Exifrxdr RExiftxdr W ExiftxrwFIFO3W XXXXXXXX-XXXXXXXX XXXXXXXX-XXXXXXXXFIFO1R FIFO2W XXXXXXXX-XXXXXXXX CONT1R/W XXXXX0XX-XXX00000XXXXXXXX-X0000000 XXXXXXXX-XXX00000 Interrupt Vector Interrupt Address of TBR Interrupt source OffsetDefault Interrupt Address of TBR Interrupt source Offset NMI Non Maskable InterruptMin Electrical CharacteristicsParameter Symbol Rating Unit ΣiolParameter Symbol Value Unit TypPin Conditions Value Unit Min Typ CfresetParameter TCK/TRST/TMS TDI/TDOPin Conditions Value Unit Input Levels High driven Vcrs standard range Usbc VDDE/2Mclko Pin Conditions Reset ParameterUnit Remarks Min Mclko ↑ RDX Mclko ↑RDY Mclko ↑ SIN1, SIN0 SCK1, SCK0SOUT1, SOUT0 Sclk ↑Internal shift clock mode Rxdv Rxclk ↑ Txen Txclk ↑Rxer Rxclk ↑ Reception Mdio Mdclk ↑ OUT →Parameter Symbol Pin Value Unit Remarks Min External ifWrite access USB interface Parameter Symbol Pin UDP, UDMFull-speed Buffer SCL Pclk 10 I2C interfacePclk SDA PclkCFCE2X, CFCE1X Card ifCFOEX, Cfiordx CFWEX, Cfiowrx Parameter SymbolValue Unit Remarks Min Max CDWEX, CfiowrxOrdering Information Part number Package RemarksPackage Dimension Memo Europe JapanNorth and South America Asia Pacific

MB91401 specifications

The Fujitsu MB91401 microcontroller is a versatile device designed for automotive applications, embedded systems, and industrial control. It belongs to the MB91400 series, known for its robustness and efficiency. This series integrates advanced features and technologies that cater to a wide variety of real-time applications.

One of the standout features of the MB91401 is its 32-bit RISC architecture, which operates at clock speeds up to 40 MHz. This high-performance core enables rapid processing and data handling, making it suitable for demanding applications. The microcontroller is equipped with a generous amount of Flash memory, allowing developers to store essential firmware and applications directly on the chip, enhancing reliability and reducing design complexity.

Another key characteristic is its extensive memory configuration, which includes SRAM for data storage and EEPROM for non-volatile data retention. This combination provides flexibility for developers, enabling them to tailor the memory allocation based on specific application requirements.

The MB91401 is designed with a focus on peripheral integration. It features multiple I/O ports, timer units, and A/D converters, making it an ideal choice for applications that require precise timing and analog signal processing. The analog-to-digital converters offer high resolution and fast conversion speeds, which are critical in automotive and industrial control systems where accuracy is paramount.

Safety is a critical consideration in automotive applications, and the MB91401 addresses this with built-in diagnostic features and error detection capabilities. These features help ensure that the application remains functional and safe under various operating conditions.

In terms of connectivity, the microcontroller supports various communication protocols, including CAN, UART, and SPI, facilitating seamless integration with other systems and devices. This is particularly important in automotive applications where communication between different electronic control units (ECUs) is essential for overall system functionality.

The Fujitsu MB91401 is also designed for low power consumption, making it suitable for battery-operated devices and energy-sensitive applications. Its various power-saving modes allow developers to optimize the system's performance while extending operational life.

In summary, the Fujitsu MB91401 is a powerful and flexible microcontroller that combines high-performance processing with extensive peripheral support and safety features. Its robust architecture and energy-efficient design make it an excellent choice for a wide range of automotive and industrial applications, promoting both reliability and innovation in embedded system development.
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